TMS320C6657: Cache coherence

Hi,

You may refer to the Processor SDK RTOS C6657: pdk_c665x_2_0_XX\packages\ti\drv\pcie\example\sample\src\pcie_sample.c,

void cache_invalidate (void *ptr, int size): let say you have another master writes into the DDR physical memory, your CPU tries to read those new data, it only reads from its cache and it always get the old data. So you need to call this API to invalidate this to mark the cache line dirty, then CPU will read from the physical memory to get the new data.

void cache_writeback (void *ptr, int size): let say your CPU wants to write some data into DDR for another master to pick it up. It only writes into the cache, you need to call this API, then data will be written into the physical memory.

Regards, Eric