AM4377: AM4377 uboot reading flash through spi is slow

AM4377 accesses flash IS25LP256D through spi0, the command line executes sf read 80000000 100000 700000
Read the 7MB package to the memory address 0x80000000 takes 120s, measure the clock and data line of the spi, the clock is 48M,
But only 1B is transmitted at a time, and there is a 15us interval between each B.
How should the read speed be increased, or how can the spi clock be continuously output?

In addition, the measurement memory clock frequency is 100M. the DDR MT41K256M16 is 1866M. How should the input clock of ddr be set?
Is it set to 0x5AC[18:8]? But now set to 50|2 or 400|23, the actual measurement ddr input side is still 100M clock,
The register has been set successfully, and M2 is 2 divided. Setting value is
const struct dpll_params dpll_ddr = {400, 23, 1, -1, 1, -1, -1}; or{50, 2, 1, -1, 2, -1, -1};

[code path]:ti_uboot_201605sdk3205\drivers\spi
static int omap3_spi_read(struct omap3_spi_priv *priv, unsigned int len,
void *rxp, unsigned long flags)
{
int i, chconf;
ulong start;
int cnt; //crsc debug

/*SF:RD 0x80000000,L7340032(w8),0x4803012c,4803013c; */
printf("SF:RD 0x%x,L%d(w%d),0x%x,%x;\n", rxp, len, priv->wordlen,
&priv->regs->channel[priv->cs].chconf, &priv->regs->channel[priv->cs].rx); //crsc debug

chconf = readl(&priv->regs->channel[priv->cs].chconf);

/* Enable the channel */
omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_EN);

chconf &= ~(OMAP3_MCSPI_CHCONF_TRM_MASK | OMAP3_MCSPI_CHCONF_WL_MASK);
chconf |= (priv->wordlen - 1) << 7;
chconf |= OMAP3_MCSPI_CHCONF_TRM_RX_ONLY;
chconf |= OMAP3_MCSPI_CHCONF_FORCE;
omap3_spi_write_chconf(priv, chconf);

writel(0, &priv->regs->channel[priv->cs].tx);

for (i = 0; i < len; i++) {
start = get_timer(0);
cnt = 0;
/* Wait till RX register contains data (RXS == 1) */
while (!(readl(&priv->regs->channel[priv->cs].chstat) &
OMAP3_MCSPI_CHSTAT_RXS)) {
if (get_timer(start) > SPI_WAIT_TIMEOUT) {
printf("SPI RXS timed out, status=0x%08x\n",
readl(&priv->regs->channel[priv->cs].chstat));
return -1;
}
cnt++;
}

if ((i%0x80000) == 0)
printf("%d;", cnt); //crsc debug

/* Disable the channel to prevent furher receiving */
if (i == (len - 1))
omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_DIS);

/* Read the data */
unsigned int *rx = &priv->regs->channel[priv->cs].rx;
if (priv->wordlen > 16)
((u32 *)rxp)[i] = readl(rx);
else if (priv->wordlen > 8)
((u16 *)rxp)[i] = (u16)readl(rx);
else
((u8 *)rxp)[i] = (u8)readl(rx);
}

if (flags & SPI_XFER_END) {
chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
omap3_spi_write_chconf(priv, chconf);
}

return 0;
}

[uboot info]：
omap3 spi speed 48000000Hz;
SF:RD 0x9ef16f98,L5(w8),0x4803012c,4803013c;
0;SF: Lock ops not supported for 9d flash
SF:RD 0x9ef16f97,L1(w8),0x4803012c,4803013c;
0;SF: Detected IS25LP256D with page size 256 Bytes, erase size 64 KiB, total 32 MiB
: returns 0
device 0 offset 0x100000, size 0x700000
SF:RD 0x80000000,L7340032(w8),0x4803012c,4803013c;
0;0;0;0;0;0;0; ...

BOOT># md 0x48030100
48030100: 0000002b 00000000 00000000 00000000 +...............
48030110: 00000015 00000001 00000000 00000000 ................
48030120: 00000001 00000000 00000004 00060000 ................
48030130: 00000000 00000000 00000000 00000000 ................
48030140: 00060000 00000000 00000000 00000000 ................
48030150: 00000000 00060000 00000000 00000000 ................
48030160: 00000000 00000000 00060000 00000000 ................

ddr clk：
CRSC># md 0x44DF2D20
44df2d20: 00000007 00000001 00000000 0003e817 ................
44df2d30: 00000000 00000000 0000022a 00000228 ........*...(...
44df2d40: 00000024 00000000 00000000 00000000 $...............
44df2d50: 00000000 00000000 00000000 00000000 ................
44df2d60: 00000007 00000001 00000000 00025817 .............X..
44df2d70: 00000201 00000000 00000000 00000000 ................
44df2d80: 00000000 00000000 00000000 00000000 ................
44df2d90: 00000000 00000000 00000000 00000000 ................
44df2da0: 00000007 00000001 00000000 00019017 ................
44df2db0: 00000221 00000000 00000221 00000000 !.......!.......
44df2dc0: 00000000 00000000 00000000 00000000 ................
44df2dd0: 00000000 00000000 00000000 00000000 ................
44df2de0: 00000007 00000001 00000000 0403c017 ................
44df2df0: 00000285 00000000 00000000 00000000 ................
44df2e00: 00000000 00000000 00000000 00000000 ................
44df2e10: 00000000 00000300 00000000 00000000 ................

thank you！