Hi!
I am testing the read speed of nand flash using the DMA mode,I found when starting the DMA transfer and finishing the transfer,there are more code processing time before real transfer and after the transfer,I watch the OE(read) signal and using a GPIO to notice the start and finsh point of DMA transfer.so I guess maybe this is caused that the code is processing in the DDR(clock is 150M),so I want to let the code process in the L1P cache,I use the demo code of cache,but we don't know weather the cache is enable.the operation is below:(I don't use the RTOS)
1. CacheEnableMAR((unsigned int)0xc0000000 NAND_DATA_BUFF_SIZE/2); //set the DDR address to the cache
/* Enable Cache */
CacheEnable(L1PCFG_L1PMODE_32K | L1DCFG_L1DMODE_32K | L2CFG_L2MODE_256K);
Is it correct?how can I do to enabel the L1P cache for the code?
One more thing：
I also try to edit the cmd file that change the map from DDR to L2,but the code processing time is not changed. Below is the cmd data: Why
// ============================================================================
// Linker Command File for Linking c674 DSP Programs
//
// These linker options are for command line linking only. For IDE linking,
// you should set your linker options in Project Properties.
// -c Link Using C Conventions
// -stack 0x1000 Software Stack Size
// -heap 0x1000 Heap Area Size
// ===========================================================================
-stack 0x1000
-heap 0x1000
// ============================================================================
// Specify the System Memory Map
// ============================================================================
MEMORY
{
L1P: o = 0x11E00000 l = 0x00008000
L1D: o = 0x11F00000 l = 0x00008000
L2: o = 0x11800000 l = 0x00040000
DDR2: o = 0xC0000000 l = 0x08000000
}
// ============================================================================
// Specify the Sections Allocation into Memory
// ============================================================================
SECTIONS
{
// .cinit > DDR2 // Initialization Tables
// .pinit > DDR2 // Constructor Tables
// .init_array > DDR2 //
// .binit > DDR2 // Boot Tables
// .const > DDR2 // Constant Data
// .switch > DDR2 // Jump Tables
// .text > DDR2 // Executable Code
// .text:_c_int00: align=1024 > DDR2 // Entrypoint
//
// GROUP (NEARDP_DATA) // group near data
// {
// .neardata
// .rodata
// .bss // note: removed fill = 0
// } > DDR2
// .far: fill = 0x0, load > DDR2 // Far Global & Static Variables
// .fardata > DDR2 // Far RW Data
// .stack > DDR2 // Software System Stack
// .sysmem > DDR2 // Dynamic Memory Allocation Area
//
// .cio > DDR2 // C I/O Buffer
// .vecs > DDR2 // Interrupt Vectors
.cinit > L2 // Initialization Tables
.pinit > L2 // Constructor Tables
.init_array > L2 //
.binit > L2 // Boot Tables
.const > L2 // Constant Data
.switch > L2 // Jump Tables
.text > L2 // Executable Code
.text:_c_int00: align=1024 > L2 // Entrypoint
GROUP (NEARDP_DATA) // group near data
{
.neardata
.rodata
.bss // note: removed fill = 0
} > L2
.far: fill = 0x0, load > L2 // Far Global & Static Variables
.fardata > L2 // Far RW Data
.stack > L2 // Software System Stack
.sysmem > L2 // Dynamic Memory Allocation Area
.cio > L2 // C I/O Buffer
.vecs > L2 // Interrupt Vectors
}
Thanks a lot.
