66AK2H06: EMIF16 access fails with DPLL 1.2GHz

Hi,

My customer is evaluating EVMK2H and connecting it with FPGA.
FPGA is connected to EMIF16.

When 66AK is running below 1.2GHz, there is no problem.
But if DPLL is configured to 1.2GHz, FPGA write access is failed.
They checked two EVMs and found one board works up to 1167.36MHz and other works up to 1044.48MHz.

Customer thought it was too fast for EMIF/FPGA access then they changed EMIF parameters to slow down the access, but results were the same.
Please see attached excel sheet for details.
66AK_DPLL.xlsx
Even when DPLL is set to 1.2GHz, read accesses from FPGA work fine and DDR accesses(read and write) are also OK.
What is the possible cause of the issue?

Thanks and regards,
Koichiro Tashiro