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CCS/TMS320C6678: EMIF read problem: External exception happened.

Peijun Zhu
Prodigy 190 points

Part Number: TMS320C6678

Tool/software: Code Composer Studio

Dear TI experts,

Single EMIF read is all right. However, when the target ram space (in FPGA) is also frequently read by the other part (eg: pci-e), CCS report:

External exception happened. MEXPFLAG[3]=0x4004000.
Event 110: MDMAERREVT XMC VBUSM error event
MDMA read status error detected
XID (Transaction ID)= 3
Timeout error
Event 122: DMC_CMPA CPU memory protection fault for L1D (and other memory read finally goes through the L1D controller)
memory protection exception caused by local access at 0x70040800
Supervisor Read violation
NRP=0x82aa30, NTSR=0x1800d, IRP=0x82aa2c, ITSR=0xd, TSCH= 0xc, TSCL= 0x8f169451
B3=0x82aa2c, A4=0x70040004, B4= 0x831b20, B14= 0x83aae8, B15= 0x83a230
Exception happened at a place can not safely return!

Could you please explain how could that happen and how can I fix it?

Thanks and regards,

Peijun

  • 0
    TI__Mastermind 30986 points
    Peijun,

    Thanks for your post. Due to the Easter Holiday in the US, we will not be able to get back to you until early next week. We're sorry for the delay.
  • 0 in reply to RonB
    TI__Guru* 95265 points
    Hi,

    What is the test code based on? Is it TI processor SDK RTOS and what release? And if the test is on TI C6678 EVM or your own board?

    For the EMIF16, you used CE0 correct? Do you use EDMA on EMIF interface or just CPU? When you said " read by the other part (eg: pci-e)", do you mean that C6678 also reads into FPGA via PCIE interface? That is you have both EMIF and PCIE interface into the FPGA. A block diagram is helpful to understand the issue. Does PCIE use EDMA or just CPU? Is reading into the same region intended?

    Will it always crash or sometimes and if the error dump always the same? Do you have any information about the CGT version and optimization? See a similar issue here: e2e.ti.com/.../518678

    Regards, Eric
  • 0 in reply to lding
    Prodigy 190 points

    Hi Eric,

    Thank you for your reply.

    PCI-E read also from PC to FPGA. And it's reading into the same region intended.

    Problem solved.

    It's about AWCCR_MAXEXTWAIT settings.

    Thank you all the same.

    Peijun