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AM3352: about RGMII layout

yimin bai34
Genius 4755 points
Part Number: AM3352

Hi SIr 

We refer to the layout guide of Sitara as below 

http://processors.wiki.ti.com/index.php/Sitara_Layout_Checklist#Ethernet_PHY_Signals

And refer to other suggestion that If the application requires longer trace length please keep it below six inches and place the trace in the middle layer.

Based on our design, the max. trace length will be over 6-inches ~6500mil.

Does Ti have any suggestion or method how to meet the rgmii timing requirement 

Thanks

BR

Yimin

  • 0
    TI__Mastermind 27890 points

    Hello Yimin,

    I'm not sure what "other suggestion" you are are referring to with regard to RGMII trace length. I do not see it mentioned in the layout guide you linked.

    Regardless, I do not expect a RGMII bus length of 6.5" to be problematic from a timing perspective. The short-trace recommendation likely stems from an effort to keep EMI to a minimum given that the RGMII bus clock is 125MHz at 1000Mb speeds. Follow best-practices for high speed layout (SPRAAR7 is a good reference), closely length match your signals, perform a timing analysis as you would for any interface and there should be no issues.