• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Subscribers 99 subscribers
  • Views 379 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320C6678: POST tests

Lucian Silistru
Prodigy 30 points

Part Number: TMS320C6678

Hi,

We are trying to add some POST tests to a TMS320C6678 based board, starting from the old C64x ones. While researching we have found pdk_c667x_n_n_nn\packages\ti\boot\ but could not find equivalents for the CPU tests for the older processor:

TEST_BA  .set  1        ;set to 0 to DISABLE "BASIC" test routine

TEST_AL  .set  1       ;set to 0 to DISABLE "ALU" test routine

TEST_MU  .set  1       ;set to 0 to DISABLE "MULT" test routine

TEST_BI  .set  1       ;set to 0 to DISABLE "BIT" test routine

TEST_SA  .set  1         ;set to 0 to DISABLE "SAT" test routine

TEST_CO  .set  1         ;set to 0 to DISABLE "COND" test routine

TEST_CI  .set  1         ;set to 0 to DISABLE "CIR" test routine

TEST_A4  .set  1        ;set to 0 to DISABLE "ALU40" test routine

TEST_SP0 .set  1        ;set to 0 to DISABLE "SPBUFFER_0" test routine

TEST_SP1 .set  1        ;set to 0 to DISABLE "SPBUFFER_1" test routine
 

Are they hidden someplace else?

Are they not needed for C66x processors?

Thank you.

Lucian Silistru

  • 0
    TI__Guru**** 161600 points
    Hi,

    I am using Processor SDK RTOS 5_02_00_10 and have the following path:
    /ti/pdk_c667x_2_0_12/packages/ti/boot/post/src

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    Prodigy 30 points
    Hi,

    Sorry for the delayed reply.

    We have found that implementation of POST and the question is related to the differences between pdk_c667x version and c64x+ version.

    In short:
    1. Chk6xTest, memTestDataBus, memTestAddressBus from c64x+ or equivalent are not implemented anymore - they test instruction set, data bus (reads specific bit patterns from the same address) and address bus (reads specific data from a range of addresses to exercise various address bus bits).
    Q: Are these test cases not included in POST for c66x because they are not needed (processor will detect errors in these areas) or because they were not ported - and could be useful if someone were to port them?

    2. c66x memory tests are documented to be non-destructive for c64x+ but are not so for c66x.
    Q: Is there a specific reason behind this or just part of c66x POST code design.

    Thank you for your time.

    Lucian Silistru
  • 0 in reply to Lucian Silistru
    TI__Guru* 95265 points

    Lucian,

    The POST wiki for Keystone I/II device is here: http://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/index_board.html#power-on-self-test

    The POST is designed as peripherals test for out of factory EVMs (like EEPROM, NAND, NOR, LED, DDR, etc). It doesn't include any CPU level (e.g instruction set test, data/address bus test). The current Processor SDK RTOS C6678 POST is under pdk_c667x_2_0_xx\packages\ti\boot\post. This is directly ported from MCSDK for C66x device: mcsdk_2_01_xx_xx\tools\post. The last MCSDK was released in Nov 2012 and obsolete.

    We don't have any plan to add test cases for instruction set, data bus (reads specific bit patterns from the same address) and address bus (reads specific data from a range of addresses to exercise various address bus bits). But you may add those functions if needed.

    The C66x memory test is the DDR memory test, code running from L2 memory. The writes/readbacks a pattern for the whole DDR range, it is the POST code design.

    Regards, Eric

  • 0 in reply to lding
    Prodigy 30 points

    Thank you for the reply and clarifications.

    It is now clear for us how to proceed with the implementation of a POST.

    Lucian Silistru