RTOS/OMAP-L138: QDMA problem with EMIF

Hello Patryk,

Are you developing on the ARM or DSP side? And are you running Linux (if on ARM) or TI-RTOS?

Can you please share your cache and MMU configuration? And where in memory are you transferring to and from, i.e, your source and destination address? If you can share your PaRAM settings that would be good too.

Also, please take a look at this thread linked below. There are some links posted in there by Mukul that you may find useful.

Regards,
Sahin

Hello Sahin,

I developing on the ARM side and I running SYS/BIOS 6.73.00.12.
I developing my project on the inherited code which was initially developed using StarterWare.
I have problem with MMU because when I try to run this an exception occurs. Therefore I have disable MMU and cache memory in *.cfg file.
I tried add varies attribute configuration for MMU but this didn't solved exception problem...

var Cache1 = xdc.useModule('ti.sysbios.family.arm.arm9.Cache');
var Mmu = xdc.useModule('ti.sysbios.family.arm.arm9.Mmu');

// Enable the cache
Cache1.enableCache = false;
// Enable the MMU (Required for L1 data caching)
Mmu.enableMMU = false;

My exception when when I turned on the MMU:

[ARM9_0] size: 0x20000.
R0 = 0x80018000  R8  = 0xc274356c
R1 = 0x00000000  R9  = 0xc275cb40
R2 = 0x00000010  R10 = 0x000001c8
R3 = 0xfffffff9  R11 = 0xffffffff
R4 = 0xc27031f0  R12 = 0x00000000
R5 = 0xc275e14e  SP(R13) = 0xc2743268
R6 = 0x00000000  LR(R14) = 0xc26d8a24
R7 = 0xc274350c  PC(R15) = 0xc26d8a2c
PSR = 0x600000df
DFSR = 0x00000005  IFSR = 0x0000001a
DFAR = 0x80018000
ti.sysbios.family.arm.exc.Exception: line 205: E_dataAbort: pc = 0xc26d8a2c, lr = 0xc26d8a24.
xdc.runtime.Error.raise: terminating execution

My PaRAM:

void QDMA_Config_PARAM_CHANNEL_0(unsigned int SRC, unsigned int DST, unsigned short CNT)
{
    QDMA_CFG_PaRAM_120->OPT_SAM         =   0x0;   
    QDMA_CFG_PaRAM_120->OPT_DAM         =   0x0;    
    QDMA_CFG_PaRAM_120->OPT_SYNCDIM     =   0x0;  
    QDMA_CFG_PaRAM_120->OPT_STATIC      =   0x0;   
    QDMA_CFG_PaRAM_120->OPT_Reserved_1  =   0x0;
    QDMA_CFG_PaRAM_120->OPT_FWID        =   0x2;    
    QDMA_CFG_PaRAM_120->OPT_TCCMODE     =   0x0;
    QDMA_CFG_PaRAM_120->OPT_TCC         =   0x0;    
    QDMA_CFG_PaRAM_120->OPT_Reserved_2  =   0x0;
    QDMA_CFG_PaRAM_120->OPT_TCINTEN     =   0x1;   
    QDMA_CFG_PaRAM_120->OPT_ITCINTEN    =   0x0;
    QDMA_CFG_PaRAM_120->OPT_TCCHEN      =   0x0;
    QDMA_CFG_PaRAM_120->OPT_ITCCHEN     =   0x0;
    QDMA_CFG_PaRAM_120->OPT_PRIVID      =   0x0;
    QDMA_CFG_PaRAM_120->OPT_Reserved_3  =   0x0;

    QDMA_CFG_PaRAM_120->SRC     =   SRC;     
    QDMA_CFG_PaRAM_120->ACNT    =   CNT; 
    QDMA_CFG_PaRAM_120->BCNT    =   0x1;
    QDMA_CFG_PaRAM_120->DST     =   DST;    
    QDMA_CFG_PaRAM_120->SRCBIDX =   0x0;
    QDMA_CFG_PaRAM_120->DSTBIDX =   0x0;
    QDMA_CFG_PaRAM_120->LINK    =   0xFFFF;
    QDMA_CFG_PaRAM_120->BCNTRLD =   0x0;
    QDMA_CFG_PaRAM_120->SRCCIDX =   0x0;
    QDMA_CFG_PaRAM_120->DSTCIDX =   0x0;
}

And Function to trigger QDMA:

void QDMA_START_CHANNEL_0(void)
{
    QDMA_CFG_ICR |= 0x1;

    QDMA_CFG_PaRAM_120->CCNT = 0x1;
}

Additionaly I added *.map file.

Best regards,
Patryk

RZ_ARM_PROJECT.txt

Hello Sahin,

Can you help me?

Hello Patryk,

Patryk_93 said:

ti.sysbios.family.arm.exc.Exception: line 205: E_dataAbort: pc = 0xc26d8a2c, lr = 0xc26d8a24. xdc.runtime.Error.raise: terminating execution

Please set a breakpoint at the LR address 0xc26d8a24. This is where the exception is occurring. You should be able to see what instruction is causing it and which address is being accessed.

There should be some MMU configuration other than Mmu.enableMMU = false, where first/second level descriptors get set. Can you share that? It may be in some startup code that occurs before main so you may need to disable the auto-run to main feature in your target configuration file and step through. I suspect the address being accessed is not in the MMU configuration which is causing the exception.

Regards,
Sahin

Hello Sahin,

Thanks for your support. I solved the problem with MMU but this didn't solve problem with DMA.

When I send more than 1464B via EMIF I looked strange things in EMIFA data bus BUT when I waiting after calling "START_QDMA" function:

while( (QDMA_CFG_IPR & 0x1) != 0x1){;}

this problem doesn't appear..

I have enabled MMU but disabled cache.

Where is the problem? I think I have a similar problem with the SD card.

Best regards,

Patryk.

Patryk,

Do you see this issue if you change the destination address to DDR? Or does it only occur with EMIF?

What is the EMIF interfacing to? If NAND Flash, the following tool would be useful for verifying timing values:
processors.wiki.ti.com/.../_AM1x

Is breaking up the large transfer into smaller transfers an option?

It looks like you were able to workaround the issue by adding a delay between transfers. Is my understanding correct?

Regards,
Sahin