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66AK2H12: MPAX setting

Kz777
Expert 7895 points

Part Number: 66AK2H12

Hi Champs,

It contain customer data. When you assign people , I will send detail data to assign people.

(Q1:) According to "SPRUGW0C" Table 7-4 document,   it is able to MPAX assign for 1GB data size.

However, we failed this assign. Do we need some action ?

We are now evaluating XMC-MPAX test. However, MPAX doesn't work depend on memory size.

Goal : Assign 1.25GB to 0x8_20000_0000 (Physical address) from 0x8000_0000 (logical address)

So, I think we have to separate address for 1.25GB as 1GB + 250MHz.

--------

Test 1 : (Failed)

Divide two address setting for 1GB + 256 MB MPAX setting 

Set logical address 0x8000_0000 => Physical address  0x8_2000_0000 (1GB)

       logical address 0xC000_0000 => Physical address 0x8_6000_0000(256MB)

Result =>  This 1GB area didn't work MPAX. Only 256MB area is working MPAX

The memory window value is 

-------------

Test 2 : (Success)

Divide three address setting for 512MB +512MB+ 256 MB MPAX setting 

Set logical address 0x8000_0000 => Physical address  0x8_2000_0000 (512MB)

       logical address 0xA000_0000 => Physical address 0x8_4000_0000(512MB)

      logical address 0xC000_0000 => Physical address 0x8_6000_0000(256MB)

Result => we changed maximum area to 512MB,  MPAX is working.

We monitor this test on the memory map

This is "Test 2" window

Regards,

Kz777

  • 0
    TI__Guru* 85625 points
    Please send the additional details and we will evaluate.
    Regards
    Mukul
  • 0 in reply to Mukul Bhatnagar
    TI__Expert 7895 points
    Hi Mukul,
    Thanks for offer.
    We found some rules as bellow.

    (1)Physical address and logic address is only able to indicate by 1GB alignment for MPAX 0x4000_0000・0x8000_0000・0xC000_0000

    It is not indicate this alignement 0xA000_0000 0x9000_0000.

    When we change alignment above rule. This issue was fixed.

    Do you have such a rules ?
  • 0 in reply to Kz777
    TI__Guru* 95265 points
    Hi Kz777,

    Below is my testing:

    1) When the K2H SOC out of reset, it has the default MPAX setup: it has a mapping of 2GB 0x8:0000:0000 to logical 0x8000:0000 (See the MPAX pair 1 (0-based)).

    0x08000000 000000BF 0000001E 800000BF 8000001E 121010FF 2101000B 00C400FF 0C400014
    0x08000020 00000080 00000000 00000080 00000000 00000080 00000000 00000080 00000000
    0x08000040 00000080 00000000 00000080 00000000 00000080 00000000 00000080 00000000

    Then I added two entries for MPAX pair 4 and 5, where 4 mapped 0x:8:2000:0000 to 0x8000:0000 with 1GB, and 5 mapped 0x8:6000:0000 to 0xc000:0000 with 256MB.
    0x08000000 000000BF 0000001E 800000BF 8000001E 121010FF 2101000B 00C400FF 0C400014
    0x08000020 820000BF 8000001D 860000BF C000001B 00000080 00000000 00000080 00000000

    I use the CCS physical view and memory view to compare the mapping. It is true that 8:6000:0000<----->c000:0000 correctly mapped. However, 8:0000:0000 <----->8000:0000. Not the newly programmed 8:2000:0000<----->8000:0000, that is the MPAX 4 didn't take effect, although it should override lower MPAX pair.

    2) To verify your idea of alignment, I deleted MPAX 1 (fill with 0).
    0x08000000 000000BF 0000001E 00000080 00000000 121010FF 2101000B 00C400FF 0C400014
    0x08000020 820000BF 8000001D 860000BF C000001B 00000080 00000000 00000080 00000000

    It didn't change the behavior. Still 0x8:0000:0000<-------->0x8000:0000

    3) Then I change the alignment, that 3 blocks each of 512MB, the alignment is also 512MB
    0x08000000 000000BF 0000001E 00000080 00000000 121010FF 2101000B 00C400FF 0C400014
    0x08000020 820000BF 8000001B 840000BF A000001B 860000BF C000001B 00000080 00000000

    The 3 regions mapping worked.

    So, it does look there is an alignment requirement. However I didn't find it in Corepac MPAX section. Let me check and update here.

    Regards, Eric
  • 0 in reply to lding
    TI__Expert 7895 points

    Hi Eric,

    Thanks for your analysis.

    Regarding MSMC comment, I found such a some rules.

    However, does this document relate XMC-MPAX too ?

     

    http://www.ti.com/lit/ug/spruhj6/spruhj6.pdf

    2.2.3 Memory Protection

     

     

    Segments are always sized to a power of two and start on a corresponding power-of-two boundary (for example, a 4 KB segment always starts on a 4 K boundary, and a 4 GB segment corresponds to the entire 32-bit address space). For the SMS port MPAX unit, the maximum allowed segment size is 16 MB (SEGSZ=10111b), which would cover the full MSMC storage space

  • 0 in reply to Kz777
    TI__Guru* 95265 points
    Hi,

    I am still checking with our engineer team.

    Regards, Eric
  • 0 in reply to lding
    TI__Expert 7895 points
    Hi Eric,
    Thanks a lot.
  • 0 in reply to Kz777
    TI__Guru* 95265 points
    Hi,

    Your usage case is if you can map physical address 0x8:2000:0000 (512MB, aligned) to logical address 0x8000:0000 with segment size 1GB? I got the feedback from the design team: input and output regions have to be address aligned properly to their segment size. So the example below wouldn’t work since the 512MB region isn’t 1GB aligned.

    Regards, Eric
  • 0 in reply to lding
    TI__Expert 7895 points
    Hi Eric,
    Thanks. We understand that our expectation is correct.