Other Parts Discussed in Thread: TLV320AIC3106
Hello,
We are planning to use AM4378 processor with SiI9022 HDMI transmitter on a custom board with video and audio output.
The TI AM437x GP EVM, which we have, uses the same HDMI transmitter so that we were trying to test the circuit before we built our custom PCB.
We successfully played audio on the EVM trough the TLV320AIC3106 codec in the LCD display mode. However, in this case I believe, the TLV320AIC3106 codec is in master mode and generates the appropriate audio clocks from the 12.000 MHz external oscillator connected to its MCLK input.
When we switched the EVM to HDMI mode, we were able to see the video output on the TV screen but there was no audio. The same 12.000 MHz external oscillator clock is provided to the SiI9022 MCLK input but it does not look like the SiI9022 can operate in master mode. We have NDA with Lattice and obtained all technical information about the part but could not find anything about setting it up in master mode.
Maybe we have not setup something correctly on the EVM but it looks like the SiI9022 cannot operate in master mode and the AM437x McASP cannot generate accurate audio clocks from the main 24 MHz oscillator. (The 12 MHz external oscillator is also not suitable for the McASP nor it is connected to the McASP high speed clock input/output pin AHCLKx)
Is my conclusion that the EVM cannot play audio through the SiI9022 HDMI port accurate?
Please let me know if any of the options below is not correct or if there is a better or simpler solution.
1. Use external 24.576 MHz oscillator connected to the AM4378 AHCLKX pin and the SiI9022 MCLK pin.
The required audio clocks are calculated as follows (assume 48 kHz Fs):
Bit-clock = 2 slots * 32 bits per slot * 48 kHz = 3.072 MHz (each frame has two slots)
Master Clock = 128 (may also be others like 192, 256, etc.) * 48 kHz = 6.144 MHz.
Then 24,576 kHz / 4 (HCLKXDIV divider) = 6.144 MHz (MCLK) / 2 (CLKXDIV divider) = 3.072 MHz Bit-clock
2. (Preferred) Use XDMA_EVENT_INTR1 pin (Ball C24) of AM4378 processor that can be configured as CLKOUT2 providing output clock from EXTDEV PLL via EXTDEV_PLL_CLKOUT, with very flexible frequency output and connect it to the AM4378 AHCLKX pin and SiI9022 MCLK pin.
The PLL output frequency formula is – (Fin / (N + 1))* M/M2 = (24 MHz / 50) * 128/10 = 6.144 MHz audio clock. (may also be higher and divided down in the McASP module)
(N – 0 - 255, M – 2 - 4095, M2 – 1 - 127) AM4378 Technical Reference Manual, rev. H, pages 273, 285, 287.
