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66AK2H12: Question about K2H DDR3B usage.

Denny%20Yang99373
Expert 3805 points

Part Number: 66AK2H12
Other Parts Discussed in Thread: SYSBIOS

Hi all,

Customer is using DDR3A and DDR3B.

1, If set the heap at DDR3B, the calloc will failed. We have test the DDR3B space, it can read/write fine. Are there any limitation for DDR3B? thanks!


2, Does PCIe can access DDR3B 512MB space or 2GB space?

thanks!

BR,
Denny

  • 0
    TI__Guru* 95265 points
    Hi Denny,

    Can you explain your mapping? Shouldn't that:

    0x60000000, 0x080000000
    0x64000000, 0x084000000 =========> why you use 0x60000000?
    ....

    For the first 64MB, it looks you divided it into 4x16 MB regions. What happens you run malloc to allocate a heap? will it return a pointer to 0x6200_0000? Or how it failed?

    For PCIE, if you use EDMA, it will be the SOC view for the address. That is only 512MB DDR3B. If you use CPU, I thought you can access the 2GB.

    Regards, Eric
  • 0 in reply to lding
    Prodigy 90 points
    Hi, it's my question.

    0x60000000, 0x080000000 =========> for core0 dsp
    0x60000000, 0x084000000 =========> for core1 dsp
    and so on. 512MB is divided equally among 8 core DSP. Each DSP has 64MB and logical address range is 0x60000000~0x63FFFFFF.

    The return value of calloc is NULL. It doesn't seem to work in DDR3B. Code and data can load into the DDR3B and work ok.
  • 0 in reply to lding
    TI__Expert 3805 points

    Hi Eric,

    Customer have test the DDR3B read/write is fine.

    And use it as program or data ram also fine.

    But all calloc/malloc not working.

    Please help to confirm if there any reason cause this. thanks!

    BR,
    Denny

  • 0 in reply to Denny%20Yang99373
    TI__Guru* 95265 points
    Denny and gq,

    Can you provide a small CCS project showing the malloc issue? The code is baremetal or SYSBIOS? Did you test this on TI K2H EVM?

    Regards, Eric
  • 0 in reply to lding
    Prodigy 90 points
    Hi Eric and Denny,

    This problem is related to DDR3B memory mapping. If the printf function is used before DDR3B memory mapping, the problem will reappear and vice versa. The prinf function seems no memory calloc used, it still bothers us.
  • 0 in reply to gq zhou
    TI__Guru* 95265 points
    gq,

    Thanks! Are you able to pass me a CCS project to reproduce and debug?

    Regards, Eric
  • 0 in reply to lding
    TI__Guru* 95265 points

    Hi,

    I didn't get any details with a project showing the problem. Here is what I did and I don't see any issue to allocate a heap from DDR3B. Please check with my explanation below and debug your own project.

    My test is based on TI K2H EVM.

    1. I have the standard GEL file to initialize the DDR3A and DDR3B.

    C66xx_0: GEL Output: DDR begin
    C66xx_0: GEL Output: XMC setup complete.
    C66xx_0: GEL Output: DDR3 PLL (PLL2) Setup ...
    C66xx_0: GEL Output: DDR3 PLL Setup complete, DDR3A clock now running at 666 MHz.
    C66xx_0: GEL Output: DDR3A initialization complete
    C66xx_0: GEL Output: DDR3 PLL Setup ...
    C66xx_0: GEL Output: DDR3 PLL Setup complete, DDR3B clock now running at 800MHz.
    C66xx_0: GEL Output: DDR3B initialization complete
    C66xx_0: GEL Output: DDR done

    2. Connect DSP core 0, it has default MPAX setting, mapping DDR3A 2GB from physical 0x0:8000_0000 to logical 0x8000:0000

    0x08000000 000000BF 0000001E 800000BF 8000001E 121010FF 2101000B 00C400FF 0C400014

    3. Now I changed the MPAX pair 1 to mapping DDR3B 512MB from physical 0x0:6000_0000 to logical 0x8000:0000 

    0x08000000 000000BF 0000001E 060000BF 8000001C 121010FF 2101000B 00C400FF 0C400014

    I was able to verify that phy and logical match

    4. I wrote a simple code to put everything in DDR3B. The heap is also inside, the alloc has no issue. Project attached.

    [C66xx_0] Hello world, pointer is allocated at address 0x80008108
    p1[0] = 0
    p1[1] = 1
    p1[2] = 4
    p1[3] = 9

    3731.simple.zip

    Regards, Eric