66AK2H12: K2H SRIO pin electrical spec

Hello,
can you check please if this document
www.ti.com/.../sprugw1c.pdf
contains information you need?
BR
Michail

Hi Michail, Thanks for looking.
Yes, I already checked this document too. However, there is no this PIN timing information and thresh hold information.

Hi ,

Could you please any update of this ?

Hello,
sorry for late response (holidays here).
For SRIO there are selectable thresholds and dedicated registers for this.
You can find more detailed description in www.ti.com/.../sprue13j.pdf
About some physical specs and signal wirings you can refer to www.ti.com/.../spraat9a.pdf
Hope this can help in your case.
BR
Michail

Hi Mark,
Thanks for your input.
I also investigated this spec.
I think this detail requirement have to obey SRIO association spec sheet according to K2H data sheet discribe comment as bellow.
However, According to this RapidIO Rev 1.3 manual, this is mentioned only mentioned 3.14Gbps.
We are using 5Gbps. Could you indicate us where mention 5Gbps use case on the Rapid I/O revision ?

From www.ti.com/.../66ak2h12.pdf
******************************************************************
11.21.1 Serial RapidIO Device-Specific Information
The approach to specifying interface timing for the SRIO Port is different from other interfaces. For these
other interfaces, the device timing was specified in terms of data manual specifications and I/O buffer
information specification (IBIS) models.
The Serial RapidIO peripheral is a master peripheral in the device. It conforms to the RapidIO™
Interconnect Specification, Part VI: Physical Layer 1×/4× LP-Serial Specification, Revision 1.3.
For the SRIO port, Texas Instruments provides a PCB solution showing two TI SRIO-enabled DSPs
connected together via a 4× SRIO link. TI has performed the simulation and system characterization to
ensure all SRIO interface timings in this solution are met.
NOTE
TI supports only designs that follow the board design guidelines outlined in the RapidIO™
Interconnect Specification, Part VI: Physical Layer 1×/4× LP-Serial Specification, Revision
1.3.
*************************************************************************************************************************

Hi Champs,
For 5Giga mode, this is Rev2.1.
So, I turned out this detail timing spec mentioned on the "RapidIO Part 6: LP-Serial Physical Layer Specification Rev. 2.1".

Does this device support above document for Rev2.1 mode , correct ?

Regards,
Kz777