AM5K2E02: Copying Rom Boot Parameter Table from flash

Dan ,

My understanding is that the ARM  ROM expects the  HEader to be in big endian and it has no dependency in the endian settings the DEVSTAT[0] should always be set as little endian for the device as that defines the endian for the SOC (DSP,  interconnect, etc)

If you have referred to the Keystone II boot examples that we provide here, the two stage and DDR based examples have a comment that explains how the image looks like and what part of the image needs to be in big endian format.  Everything market BE refers to big endian.

#############################################################################################	
#	Stage 1, DDR Config, and Stage 2 combined 
#		|--------------------------------------------------------------------------------------|
#		|	CCS Header (1651 1 %Address(LE)% 1 %Length%) 		|	Stripped off by the make step above
#		|--------------------------------------------------------------------------------------|		
#		|	Stage 1 GPHDR Length 	(BE 32 bits) 				        |	<-- Loaded into the SPI Flash starting at 0x0000_0000		
#		|--------------------------------------------------------------------------------------|		
#		|	Stage 1 GPHDR Address	(BE 32 bits) (0x0C00_0000)   |		
#		|--------------------------------------------------------------------------------------|		
#		|	Stage 1 Data 0									|	<-- Copied by the RBL to the Address specified in the GPHDR (0x0C00_0000)	
#		|	Stage 1 Data 1									|		
#		|	.....												|		The only thing that this stage 1 program does is change the boot parameter table 
#		|	Stage 1 Data (Length - 2)							|		to use the address 0x0000_1000 (loaded with the DDR config below) for the spi 
#		|	Stage 1 Data (Length - 1)							|		boot branch address, update the PLLs, Change the SPI speed, and then re-enter the boot code
#		|--------------------------------------------------------------------------------------|		
#		|	Stage 1 GPTLR Length	(0x00000000)				        |	<-- This GPTLR of all zeroes tells the RBL that data transfer is finished		
#		|--------------------------------------------------------------------------------------|			
#		|	Stage 1 GPTLR Address	(0x00000000)				|	<-- Once data transfer is finished the RBL branches the ARM core to the Address that the final section was loaded to (0x0C00_0000)	
#		|--------------------------------------------------------------------------------------|		
#		|	Padding											|		
#		|	Padding											|		
#		|	.....												|		
#		|	Padding											|		
#		|	Padding (This location - Data 0 location) = 0x1000	        |		
#		|--------------------------------------------------------------------------------------|		
#		|	DDR Config GPHDR Length (BE 32 bits)        		        |	<-- Loaded into the SPI Flash starting at 0x0000_1000 because of the padding
#		|--------------------------------------------------------------------------------------|
#		|	DDR Config GPHDR Address(BE 32 bits) (0x0C1A6E00) 	|
#		|--------------------------------------------------------------------------------------|
#		|	DDR Config Data 0									|	<-- This section is loaded into the DDR config table in the MSMC located at 0x0C1A6E00
#		|	DDR Config Data 1									|		The RBL checks the DDR config table at the end of every section transfer and once it 
#		|	.....												|		becomes non-zero the values loaded there are immediately used to configure the DDR for use
#		|	DDR Config Data (Length - 2)						        |		allowing the next section to be copied directly to DDR if necessary
#		|	DDR Config Data (Length - 1)						        |	<-- Once the RBL finishes copying this section it will use the config data to set up the DDR
#		|--------------------------------------------------------------------------------------|
#		|	Stage 2 GPHDR Length 	(BE 32 bits)        		                |		
#		|--------------------------------------------------------------------------------------|		
#		|	Stage 2 GPHDR Address	(BE 32 bits) (0x8000_1000)	|		
#		|--------------------------------------------------------------------------------------|		
#		|	Stage 2 Data 0									|	<-- This section is copied straight into DDR becuase the previous section configured the DDR for use		
#		|	Stage 2 Data 1									|		This program writes test values to memory, switches the ARM master core to big endian, writes the 
#		|	.....												|		same test values to memory, then switches back to little endian mode and writes the same test values
#		|	Stage 2 Data (Length - 2)							|		one more time. The program then goes and populates the bootMagicAddress of all four DSP cores and sends
#		|	Stage 2 Data (Length - 1)							|		them an IPC interrupt to branch them to an idle instruction. The ARM master core then powers on the slave
#		|--------------------------------------------------------------------------------------|		ARM core and writes the address of an idle loop into its magicAddress. The ARM master then idles.
#		|	Stage 2 GPTLR Length	(0x00000000)				        |<-- This GPTLR of all zeroes tells the RBL that data transfer is finished
#		|--------------------------------------------------------------------------------------|		
#		|	Stage 2 GPTLR Address	(0x00000000)				|	<-- Once data transfer is finished the RBL branches the ARM core to the Address that the final section was loaded to (0x8000_1000)		
#		|--------------------------------------------------------------------------------------|		
#############################################################################################		

Here is an additional comment that I see in the ROM spec:

Boot parameter tables for every boot mode all begin with the same 7 parameters. For legacy reasons every parameter is a 16 bit value. In some tables where a 32 bit value is shown it implies that there are two 16 bit values, with the most significant word at the lowest offset (big endian format regardless of the endianness of the device).

The way the examples implement boot parameter table, we don`t append it to the image instead we use stage 1 to place the boot parameter table in the RAM and then re-enter into Boot ROM so the boot uses the new boot media configuration but what you are trying to achieve should also be feasible.

Hope this helps. 

Regards,

Rahul

The boot configuration pins are the BOOTMODE pins which gets latched into DEVTSAT register. Section 8.1.2 is dedicated for pins that are using to configure the initial boot parameter table. Table 5-2 in the datasheet talks about the pin names for these signals. You will notice that many of the boot modes have a BOOTMODE[4] as a Min pin, in this case the BootROM picks up predetermined defaults. These defaults are marked in the data sheet for each boot mode.

Refer to Table8-19, which describes the SPI boot parameter table. Read Addr MSW and Read Addr LSW is used to read the image from specific SPI flash address. You can take a look at the the multistage example for SPI boot mode in Keystone II Boot examples then you will see that stage 1 places new boot parameter structure and DDR configuration table and then re-enters in to ROM boot. The new SPI boot parameter table used in stage 1 can be found here:
git.ti.com/.../paramTables.h

The SPI flash offset is configured as 0x1000 for the second stage to be loaded. Please review the example code and let us know if there are any further questions.
processors.wiki.ti.com/.../KeystoneII_Boot_Examples

Regards,
Rahul