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Linux/AM5708: GPMC timing parameters calculation for external FPGA/NVSRAM interface

Narayanan Govind
Prodigy 120 points
Part Number: AM5708

Tool/software: Linux

Hi,

We are struggling to communicate with FPGA/NVSRAM interface via GPMC due to multiple issues and clearing one by one with your team support via forum.

We are able to read FPGA/NVSRAM but filled with random values which are not expected.

Observations for FPGA interface:

================================

root@am57xx-evm:~# devmem2 0x12000784 w
/dev/mem opened.
Memory mapped at address 0xb6f07000.
Read at address  0x12000784 (0xb6f07784): 0xA330A330
root@am57xx-evm:~# devmem2 0x12000784 w 0xaaaaaaaa
/dev/mem opened.
Memory mapped at address 0xb6f2b000.
Read at address  0x12000784 (0xb6f2b784): 0xA330A330
Write at address 0x12000784 (0xb6f2b784): 0xAAAAAAAA, readback 0xAAAAAAAA

I tried to read 0x12000784 location and it is filled with 0xA330A330(remaining FPGA locations are also filled with same value: 0XA330A330). Tried to write 0xaaaaaaaa to same location 0x12000784 and able to read same value.

My Question:

1. What might be the reason for all FPGA locations filled with 0XA330A330? is FPGA not properly programmed? or timing configurations are not proper to read FPGA registers? If timings are not proper please share us the way to calculate timing parameters used to filled with device tree properties for GPMC.

Observations for NVSRAM interface:

================================

root@am57xx-evm:~# devmem2 0x13500000 w
/dev/mem opened.
Memory mapped at address 0xb6f19000.
Read at address  0x13500000 (0xb6f19000): 0x30303030
root@am57xx-evm:~# devmem2 0x13500000 w 0X55555555
/dev/mem opened.
Memory mapped at address 0xb6f9c000.
Read at address  0x13500000 (0xb6f9c000): 0x30303030
Write at address 0x13500000 (0xb6f9c000): 0x55555555, readback 0x55555555
root@am57xx-evm:~#

After power OFF and ON controller,

root@am57xx-evm:~# devmem2 0x13500000 w           
/dev/mem opened.
Memory mapped at address 0xb6f88000.
Read at address  0x13500000 (0xb6f88000): 0x30303030
root@am57xx-evm:~#

I tried to read 0x13500000 location and it is filled with 0x30303030(remaining NVSRAM locations are also filled with same value: 0X30303030). Tried to write 0x55555555 to same location 0x13500000 and able to read same value but after power OFF and ON controller not able to get 0x55555555 and saw same random value 0x30303030.

My Question:

1. What might be the reason for all NVSRAM locations filled with 0X30303030? Are we really writing into NVSRAM region? Are  timing configurations proper to read/write NVSRAM ? If  not proper please share us the way to calculate timing parameters used to filled with device tree properties for GPMC.

Note: Tried to contact FPGA/NVSRAM device provider for timing parameters and they suggested us to go through their device manual. We didn't find any values suitable to fill device tree gpmc timing parameters.

www.microsemi.com/.../130708-proasic-sup-u-plus-u-sup-flash-family-fpgas-datasheet..

www.cypress.com/.../download...

Best Regards,

Narayanan

  • 0
    TI__Mastermind 41005 points
    Hello Narayanan,

    Could you please share the register dump for GPMC_CONFIG<1-7> for the chip select that you are using?

    Regards,
    Krunal
  • 0 in reply to Krunal Bhargav34
    Prodigy 120 points
    Hello Krunal,

    For FPGA using CS2 and below are respective GPMC_CONFIG
    root@am57xx-evm:~# devmem2 0x500000c0
    /dev/mem opened.
    Memory mapped at address 0xb6fd8000.
    Read at address 0x500000C0 (0xb6fd80c0): 0x00001000===>GPMC_CONFIG1
    root@am57xx-evm:~# devmem2 0x500000c4
    /dev/mem opened.
    Memory mapped at address 0xb6f6e000.
    Read at address 0x500000C4 (0xb6f6e0c4): 0x00181600====>GPMC_CONFIG2
    root@am57xx-evm:~# devmem2 0x500000c8
    /dev/mem opened.
    Memory mapped at address 0xb6f03000.
    Read at address 0x500000C8 (0xb6f030c8): 0x00080800======>GPMC_CONFIG3
    root@am57xx-evm:~# devmem2 0x500000cc
    /dev/mem opened.
    Memory mapped at address 0xb6f07000.
    Read at address 0x500000CC (0xb6f070cc): 0x160B160B======>GPMC_CONFIG4
    root@am57xx-evm:~# devmem2 0x500000d0
    /dev/mem opened.
    Memory mapped at address 0xb6fca000.
    Read at address 0x500000D0 (0xb6fca0d0): 0x00161616======>GPMC_CONFIG5
    root@am57xx-evm:~# devmem2 0x500000d4
    /dev/mem opened.
    Memory mapped at address 0xb6fb7000.
    Read at address 0x500000D4 (0xb6fb70d4): 0x960000C0=====>GPMC_CONFIG6
    root@am57xx-evm:~# devmem2 0x500000d8
    /dev/mem opened.
    Memory mapped at address 0xb6fcf000.
    Read at address 0x500000D8 (0xb6fcf0d8): 0x00000F52=====>GPMC_CONFIG7

    For NVSRAM using CS3 and below are respective GPMC_CONFIG
    root@am57xx-evm:~# devmem2 0x500000f0 w
    /dev/mem opened.
    Memory mapped at address 0xb6ff6000.
    Read at address 0x500000F0 (0xb6ff60f0): 0x00000000===>GPMC_CONFIG1
    root@am57xx-evm:~# devmem2 0x500000f4
    /dev/mem opened.
    Memory mapped at address 0xb6fdd000.
    Read at address 0x500000F4 (0xb6fdd0f4): 0x000F0F00===>GPMC_CONFIG2
    root@am57xx-evm:~# devmem2 0x500000f8
    /dev/mem opened.
    Memory mapped at address 0xb6fa9000.
    Read at address 0x500000F8 (0xb6fa90f8): 0x00030300===>GPMC_CONFIG3
    root@am57xx-evm:~# devmem2 0x500000fc
    /dev/mem opened.
    Memory mapped at address 0xb6efe000.
    Read at address 0x500000FC (0xb6efe0fc): 0x06060F04===>GPMC_CONFIG4
    root@am57xx-evm:~# devmem2 0x50000100
    /dev/mem opened.
    Memory mapped at address 0xb6fa5000.
    Read at address 0x50000100 (0xb6fa5100): 0x000C1010===>GPMC_CONFIG5
    root@am57xx-evm:~# devmem2 0x50000104
    /dev/mem opened.
    Memory mapped at address 0xb6f5a000.
    Read at address 0x50000104 (0xb6f5a104): 0x8C000080===>GPMC_CONFIG6
    root@am57xx-evm:~# devmem2 0x50000108
    /dev/mem opened.
    Memory mapped at address 0xb6f17000.
    Read at address 0x50000108 (0xb6f17108): 0x00000F53===>GPMC_CONFIG7
    root@am57xx-evm:~#

    Best Regards,
    Narayanan
  • 0 in reply to Narayanan Govind
    TI__Mastermind 41005 points

    Hello,

    Based on the following wiki, please take a look at Rule# 7 and 8. In your case, WEOFFTIME must be be greater than WRACCESSTIME+1. Also, WrCycleTime must be strictly greater than CsWrOffTime. Try the above settings for CS2 and update me with the results.

    Regards,

    Krunal

  • 0 in reply to Krunal Bhargav34
    Prodigy 120 points
    Thanks Krunal,

    I will update results but it seems document explains about synchronous access but our case is asynchronous and how to find GPMC_FCLK for our board?

    Best Regards,
    Narayanan
  • 0 in reply to Narayanan Govind
    TI__Mastermind 41005 points
    Hi Narayanan,

    A few of those rules will apply for asynchronous system and GPMC_FCLK for AM57xx device is 266MHz.

    Regards,
    Krunal
  • 0 in reply to Krunal Bhargav34
    Prodigy 120 points
    Thanks Krunal,

    How to GPMCFCLKDIVIDER value through device tree node?

    Best Regards,
    Narayanan
  • 0 in reply to Narayanan Govind
    TI__Mastermind 41005 points
    Hi Narayanan,

    Please navigate to the file omap-gpmc.c and look for the function "gpmc_ns_to_ticks" and "gpmc_ticks_to_ns". By default, CS is set to 0 and you can change it to your preference. However, for you system (asynchronous ) this is not needed unless you are running into the problem defined in the TRM section "Wait Monitoring During Asynchronous Read Access".

    Regards,
    Krunal