RTOS/TDA2PXEVM: LISA and DMM EMIF register configuration for 2GB per EMIF (Tolal 4GB DDR3)

Raj Veer

Intellectual 270 points

Part Number: TDA2PXEVM
Other Parts Discussed in Thread: SYSBIOS

Tool/software: TI-RTOS

Hi,

We are using VSDK3.03 source on Tda2px EVM C rev based customized HW.

Here, we are using 4GB Micron DDR3. For this ,we have configured LISA and DMM EMIF register as below mentioned :

ti_components/drivers/pdk_01_09_00_17/packages/ti/boot/sbl_auto/sbl_utils/src/tda2xxsbl_utils_tda2px_ddr_config.c

#if (TDA2XX_EMIF_MODE == SBLLIB_DUAL_EMIF_2X1GB)

{

SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO,

" Two EMIFs 1GB each (Total = 2GB)\n");

/* MA_LISA_MAP_i */

HW_WR_REG32(SOC_MA_MPU_CONF_REGS_BASE + LISA_MAP_0, 0x80700200U);

HW_WR_REG32(SOC_MA_MPU_CONF_REGS_BASE + LISA_MAP_1, 0xC0700100U);

/* DMM_LISA_MAP_i */

HW_WR_REG32(SOC_DMM_CONF_REGS_BASE + LISA_MAP_0, 0x80700200U);

HW_WR_REG32(SOC_DMM_CONF_REGS_BASE + LISA_MAP_1, 0xC0700100U);

}

#endif

As we know that SYSBIOS has an 1GB DDR size limitation on per EMIF so , Is there any implication if we configure 2GB on per EMIF when we have total 4GB DDR size?

What is pros/cons , If we configure 1GB DDR on per EMIF even though we have availability of 2GB DDR on per EMIF ?

Can we configure like as LISA_MAP_0 – >EMIF2 and + LISA_MAP_1 -> EMIF1 ,this order makes any impact?

What will be advantage when we configure interleaved LISA map in MA_LISA_MAP and DMM_LISA_MAP ?

Will it impact on performance ?

Regards

Raj

over 6 years ago

0 Rishabh Garg over 6 years ago

TI__Guru 55685 points

Hi,

Interleaving gives better performance as compared to non interleaved.
Please refer to chapter 18 of this app note for detailed explanation: www.ti.com/.../sprac21.pdf
Also swapping order does not have any impact.

Regards,
Rishabh

0 Raj Veer over 6 years ago in reply to Rishabh Garg

Intellectual 270 points

Hi Rishabh,

Thanks for reply.

Is there any cons or issue if we configure 1GB DDR on per EMIF even though we have availability of 2GB DDR3 on per EMIF (Total 4GB DDR3 size )?

Does VSDK3.06 supports 2GB per EMIF ?

Regards
Raj

0 Rishabh Garg over 6 years ago in reply to Raj Veer

TI__Guru 55685 points

Hi Raj,

There are no cons. You will have less memory space available to use or in other words some memory will remain unused.

2 GB per EMIF is LISA map setting and is supported by HW.
Vision SDK by default does not have any memory map for 2 GB per EMIF.

Regards,
Rishabh

0 Raj Veer over 6 years ago in reply to Rishabh Garg

Intellectual 270 points

Hi Rishabh,

My understanding is , even though HW supports 2GB per EMIF and SYSBIOS supports up to 1GB per EMIF ,so total 2GB.

Is this correct ?

Regards
Raj

0 Rishabh Garg over 6 years ago in reply to Raj Veer

TI__Guru 55685 points

Hi Raj,

I would suggest you to check with your System Architect with the memory requirements of your use case.
On M4 SYSBIOS supports only AMMU and not L2 MMU, so you can have max 1 GB DDR.
On A15 you can map upto 4 GB DDR.

Regards,
Rishabh

0 Raj Veer over 6 years ago in reply to Rishabh Garg

Intellectual 270 points

Hi Rishabh,

Regarding use case memory requirements, we will definitely check with our system architect

Our question is Can SYSBIOS supports 2GB per EMIF or not ?
If supports what is the configuration for:
case 1: Interleaved ?
case 2: Non interleaved ?

Please provide your reply on this.

Best Regards,
Veer

0 Rishabh Garg over 6 years ago in reply to Raj Veer

TI__Guru 55685 points

Hi Raj,

As I have already explained this is not a SYSBIOS constraint.
You need to set the LISA map registers in SBL.
You can choose both interleaved and non interleaved.

Regards,
Rishabh

0 Raj Veer over 6 years ago in reply to Rishabh Garg

Intellectual 270 points

Hi ,

We are trying to modify 512MB Bios Memory map to 2GB Bios Memory map (1GB per EMIF) . Size of 4GB DDR3 is mounted on TDA2pX HW and per EMIF interface has 2GB DDR3.

As per VisionSDK_UserGuide_MemoryMap doc reference ,we made below mentioned changes :

diff --git a/apps/build/tda2px/mem_segment_definition_bios.xs b/apps/build/tda2px/mem_segment_definition_bios.xs
index 2c5fdd9..23ac426 100755
--- a/apps/build/tda2px/mem_segment_definition_bios.xs
+++ b/apps/build/tda2px/mem_segment_definition_bios.xs
@@ -18,7 +18,7 @@ function getMemSegmentDefinition_external(core)
MB=KB*KB;

DDR3_ADDR = 0x80000000;
- DDR3_SIZE = 512*MB;
+ DDR3_SIZE = 2048*MB;

/*
* In case of ECC_FFI_INCLUDE, DDR3_BASE_ADDR_1 and DDR3_BASE_SIZE_1
@@ -27,7 +27,7 @@ function getMemSegmentDefinition_external(core)
* If this DDR3_BASE_SIZE_0 is changed, update Ipu1_0.cfg
*/
DDR3_BASE_ADDR_0 = DDR3_ADDR;
- DDR3_BASE_SIZE_0 = 508*MB;
+ DDR3_BASE_SIZE_0 = 1008*MB;

/* The start address of the second mem section should be 16MB aligned.
* This alignment is a must as a single 16MB mapping is used for EVE
@@ -42,7 +42,7 @@ function getMemSegmentDefinition_external(core)
* in non-cached virtual address of
* DDR3_BASE_ADDR_1 + 512*MB
*/
- DDR3_BASE_ADDR_1 = DDR3_BASE_ADDR_1+512*MB;
+ /* DDR3_BASE_ADDR_1 = DDR3_BASE_ADDR_1+512*MB; */
}

DSP1_L2_SRAM_ADDR = 0x40800000;
diff --git a/apps/configs/tda2px_evm_bios_all/cfg.mk b/apps/configs/tda2px_evm_bios_all/cfg.mk
index 77c430c..a3119b3 100755
--- a/apps/configs/tda2px_evm_bios_all/cfg.mk
+++ b/apps/configs/tda2px_evm_bios_all/cfg.mk
@@ -31,7 +31,8 @@ VSDK_BOARD_TYPE=TDA2PX_EVM
DUAL_A15_SMP_BIOS=no

# Supported values: DDR_MEM_512M
-DDR_MEM=DDR_MEM_512M
+DDR_MEM=DDR_MEM_1024M
+EMIFMODE=DUAL_EMIF_2X1GB

# Supported values: ipu1_0 ipu1_1 a15_0 none
NDK_PROC_TO_USE=a15_0
diff --git a/links_fw/src/rtos/bios_app_common/tda2px/a15_0/a15_0.cfg b/links_fw/src/rtos/bios_app_common/tda2px/a15_0/a15_0.cfg
index efa9900..24ddfcb 100755
--- a/links_fw/src/rtos/bios_app_common/tda2px/a15_0/a15_0.cfg
+++ b/links_fw/src/rtos/bios_app_common/tda2px/a15_0/a15_0.cfg
@@ -146,7 +146,7 @@ attrs1.shareable = 2; // sharerable
attrs1.attrIndx = 2; // Cached, normal memory

// Set the descriptor for each entry in the address range
-for (var i=0x80000000; i < 0xA0000000; i = i + 0x00200000) {
+for (var i=0x80000000; i < 0xC0000000; i = i + 0x00200000) {
// Each 'BLOCK' descriptor entry spans a 2MB address range
Mmu.setSecondLevelDescMeta(i, i, attrs1);
}
@@ -160,9 +160,9 @@ attrs2.shareable = 2; // sharerable
attrs2.attrIndx = 0; // Non-cache, normal memory

// Set the descriptor for each entry in the address range
-for (var i=0xA0000000; i < 0xC0000000; i = i + 0x00200000) {
+for (var i=0xA0000000; i <= 0xFFFFFFFF; i = i + 0x00200000) {
// Each 'BLOCK' descriptor entry spans a 2MB address range
- Mmu.setSecondLevelDescMeta(i, i-0x20000000, attrs2);
+ Mmu.setSecondLevelDescMeta(i, i, attrs2);
}

// Region for NDK packet data buffers.
diff --git a/links_fw/src/rtos/bios_app_common/tda2px/ipu1_0/Ammu1_bios.cfg b/links_fw/src/rtos/bios_app_common/tda2px/ipu1_0/Ammu1_bios.cfg
index a9e30ed..a3a39fe 100755
--- a/links_fw/src/rtos/bios_app_common/tda2px/ipu1_0/Ammu1_bios.cfg
+++ b/links_fw/src/rtos/bios_app_common/tda2px/ipu1_0/Ammu1_bios.cfg
@@ -204,7 +204,7 @@ function init()
entry.pageEnabled = AMMU.Enable_YES;
entry.translationEnabled = AMMU.Enable_YES;
entry.logicalAddress = 0xA0000000;
- entry.translatedAddress = 0x80000000;
+ entry.translatedAddress = 0xA0000000;
entry.size = AMMU.Large_512M;
entry.L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
entry.L1_posted = AMMU.PostedPolicy_NON_POSTED;
diff --git a/links_fw/src/rtos/bios_app_common/tda2px/ipu2/Ammu2_bios.cfg b/links_fw/src/rtos/bios_app_common/tda2px/ipu2/Ammu2_bios.cfg
index f7ca5f8..60aa355 100755
--- a/links_fw/src/rtos/bios_app_common/tda2px/ipu2/Ammu2_bios.cfg
+++ b/links_fw/src/rtos/bios_app_common/tda2px/ipu2/Ammu2_bios.cfg
@@ -204,13 +204,13 @@ function init()
entry.pageEnabled = AMMU.Enable_YES;
entry.translationEnabled = AMMU.Enable_YES;
entry.logicalAddress = 0xA0000000;
- entry.translatedAddress = 0x80000000;
+ entry.translatedAddress = 0xA0000000;
entry.size = AMMU.Large_512M;
entry.L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
entry.L1_posted = AMMU.PostedPolicy_NON_POSTED;
entry.L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
entry.L2_posted = AMMU.PostedPolicy_NON_POSTED;
-/*
+
var entry = AMMU.largePages[3];
entry.pageEnabled = AMMU.Enable_YES;
entry.translationEnabled = AMMU.Enable_YES;
@@ -221,5 +221,5 @@ function init()
entry.L1_posted = AMMU.PostedPolicy_NON_POSTED;
entry.L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
entry.L2_posted = AMMU.PostedPolicy_NON_POSTED;
-*/
-}
\ No newline at end of file
+
+}
diff --git a/links_fw/src/rtos/links_ipu/system/system_bsp_init.c b/links_fw/src/rtos/links_ipu/system/system_bsp_init.c
index 0c05d90..c077f92 100644
--- a/links_fw/src/rtos/links_ipu/system/system_bsp_init.c
+++ b/links_fw/src/rtos/links_ipu/system/system_bsp_init.c
@@ -291,10 +291,10 @@ Int32 System_bspInit(void)
vpsInitPrms.virtBaseAddr = 0x80000000U;
vpsInitPrms.physBaseAddr = 0x80000000U;
#else
- vpsInitPrms.virtBaseAddr = 0xA0000000U;
+ vpsInitPrms.virtBaseAddr = 0x80000000U;
vpsInitPrms.physBaseAddr = 0x80000000U;
/* if Virtual address != Physical address then enable translation */
- vpsInitPrms.isAddrTransReq = TRUE;
+ vpsInitPrms.isAddrTransReq = FALSE;
#endif
Vps_printf(" SYSTEM: VPDMA Descriptor Memory Address translation"
" ENABLED [0x%08x -> 0x%08x]\n",
--

In SBL ,we have tried below mentioned modification for DDR3 interleaved and Non interleaved LISA mapping configuration:

DDR interleaved configuration:
we are configuring interleaved DDR as below mentioned :
#if (TDA2XX_EMIF_MODE == SBLLIB_DUAL_EMIF_2X1GB)
{
…
#if 1
/* MA_LISA_MAP_i */
HW_WR_REG32(SOC_MA_MPU_CONF_REGS_BASE + LISA_MAP_0, 0x80740300U);
HW_WR_REG32(SOC_MA_MPU_CONF_REGS_BASE + LISA_MAP_1, 0x80740300U);
/* DMM_LISA_MAP_i */
HW_WR_REG32(SOC_DMM_CONF_REGS_BASE + LISA_MAP_0, 0x80740300U);
HW_WR_REG32(SOC_DMM_CONF_REGS_BASE + LISA_MAP_1, 0x80740300U);
#endif

OR

DDR non interleaved configuration:
#if (TDA2XX_EMIF_MODE == SBLLIB_DUAL_EMIF_2X1GB)
{
…
#if 1

/* MA_LISA_MAP_i */
HW_WR_REG32(SOC_MA_MPU_CONF_REGS_BASE + LISA_MAP_0, 0x80600200U);
HW_WR_REG32(SOC_MA_MPU_CONF_REGS_BASE + LISA_MAP_1, 0xC0600100U);
/* DMM_LISA_MAP_i */
HW_WR_REG32(SOC_DMM_CONF_REGS_BASE + LISA_MAP_0, 0x80600200U);
HW_WR_REG32(SOC_DMM_CONF_REGS_BASE + LISA_MAP_1, 0xC0600100U);
#endif

DDR Timing Parameters-
Presently we are using the timing parameters available in the default code.

SBL and appimage with above changes loaded successfully.

Can you please check above configuration is fine ?

Especially a15, Ammu1 and Ammu2 cfg files
Is the below changes causing any overlap ?
G:

// Set the descriptor for each entry in the address range
-for (var i=0x80000000; i < 0xA0000000; i = i + 0x00200000) {
+for (var i=0x80000000; i < 0xC0000000; i = i + 0x00200000) {
// Each 'BLOCK' descriptor entry spans a 2MB address range
Mmu.setSecondLevelDescMeta(i, i, attrs1);
}
@@ -160,9 +160,9 @@ attrs2.shareable = 2; // sharerable
attrs2.attrIndx = 0; // Non-cache, normal memory

// Set the descriptor for each entry in the address range
-for (var i=0xA0000000; i < 0xC0000000; i = i + 0x00200000) {
+for (var i=0xA0000000; i <= 0xFFFFFFFF; i = i + 0x00200000) {
// Each 'BLOCK' descriptor entry spans a 2MB address range
- Mmu.setSecondLevelDescMeta(i, i-0x20000000, attrs2);
+ Mmu.setSecondLevelDescMeta(i, i, attrs2);
}

Regards
Raj

0 Rishabh Garg over 6 years ago in reply to Raj Veer

TI__Guru 55685 points

Hi Raj,

There are multiple threads where I have answered similar questions.
Can you please check them.

Regards,
Rishabh

0 Raj Veer over 6 years ago in reply to Rishabh Garg

Intellectual 270 points

Hi Rishabh,

Thank you for reply.

As per your comment , I tried to find information in below mentioned e2e links
e2e.ti.com/.../791877
e2e.ti.com/.../2925658
e2e.ti.com/.../2922336

but unluckily, I didn’t get relevant information.

Here, I am trying to find that what should be a valid addressed range for cached and non-cached memory for 1GB and 2GB BIOS memory map for a15_0, ipu1_0 (Ammu1) and ipu2 (Ammu2) core.

Please let me know your valuable input or post specific link, which I missed.

Regards
Raj

0 Rishabh Garg over 6 years ago in reply to Raj Veer

TI__Guru 55685 points

Hi,

You can make region from 0x8000_0000 to 0x9FFF_FFFF as cached and 0xA000_0000 to 0xBFFF_FFFF as non cached.

Regards,
Rishabh

0 Rishabh Garg over 6 years ago in reply to Rishabh Garg

TI__Guru 55685 points

Hi Raj,

Are you still facing this issue?

Regards,
Rishabh

0 Raj Veer over 6 years ago in reply to Rishabh Garg

Intellectual 270 points

Hi Rishabh,

Thank you for input.

As per your input, I have tried below mentioned cached and non-cached address range for 2GB Bios Memory map for TDA2px

Address region from 0x8000_0000 to 0x9FFF_FFFF as cached -512 MB

and

Address region from 0xA000_0000 to 0xBFFF_FFFF as non-cached -512-MB

It’s working fine.

For default 512 MB BIOS memory, cached address region is configured from 0x8000_0000 to 0xA0000000 and non-cached is configured from 0xA000_0000 to 0xC0000000.

Here,i find that , we configured same 512 MB size of memory for cached and non-cached for both above mentioned case.

Is there any dependency on total size of (2GB/1GB/512MB) Bios Memory map for cached & non-cached address range config ?

Regards
Raj

0 Rishabh Garg over 6 years ago in reply to Raj Veer

TI__Guru 55685 points

Hi Raj,

There are some specific shared regions that need to be non-cached.
Can you refer to PROCESSOR_SDK_VISION_03_06_00_00\vision_sdk\apps\build\tda2px\mem_segment_definition_bios.xs for details.

Regards,
Rishabh

0 Rishabh Garg over 6 years ago in reply to Rishabh Garg

TI__Guru 55685 points

The sections that are non cached are:

SR0_ADDR                    = DDR3_BASE_ADDR_1;
REMOTE_LOG_ADDR             = SR0_ADDR              + SR0_SIZE;
LINK_STATS_ADDR             = REMOTE_LOG_ADDR       + REMOTE_LOG_SIZE;
SYSTEM_IPC_SHM_ADDR         = LINK_STATS_ADDR       + LINK_STATS_SIZE;
HDVPSS_DESC_ADDR            = SYSTEM_IPC_SHM_ADDR   + SYSTEM_IPC_SHM_SIZE;
OPENVX_SHM_ADDR             = HDVPSS_DESC_ADDR      + HDVPSS_DESC_SIZE;

Regards,

Rishabh

0 Raj Veer over 6 years ago in reply to Rishabh Garg

Intellectual 270 points

Hi Rishabh,

Thank you for support.

Need favour from you .Could you please review attached patch ,which I created to modify a BIOS memory map from default 512MB to 2GB

Fullscreen 0001-DDR3-interleaving-mode-enabled.patch.txt Download

From b97459fdf6736cdd680cf839f587cc95c9c96731 Mon Sep 17 00:00:00 2001
Date: Tue, 21 May 2019 09:02:39 +0000
Subject: [PATCH] DDR3 interleaving mode enabled

   DDR3 interleaving mode enabled

---
 .../src/tda2xx/harman_sbl_utils_tda2px_ddr_config_proto_A.c    | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/ti_components/drivers/FFC_ProtoA_board/packages/ti/boot/har_sbl_auto/sbl_utils/src/tda2xx/harman_sbl_utils_tda2px_ddr_config_proto_A.c b/ti_components/drivers/FFC_ProtoA_board/packages/ti/boot/har_sbl_auto/sbl_utils/src/tda2xx/harman_sbl_utils_tda2px_ddr_config_proto_A.c
index ed5f60e..f5633ec 100755
--- a/ti_components/drivers/FFC_ProtoA_board/packages/ti/boot/har_sbl_auto/sbl_utils/src/tda2xx/harman_sbl_utils_tda2px_ddr_config_proto_A.c
+++ b/ti_components/drivers/FFC_ProtoA_board/packages/ti/boot/har_sbl_auto/sbl_utils/src/tda2xx/harman_sbl_utils_tda2px_ddr_config_proto_A.c
@@ -484,14 +484,14 @@ static void TDA2Px_set_lisa_maps(void)
     {
 
         SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO,
-                     "       Two EMIFs 1GB each (Total = 2GB)\n");
+                     "       Two EMIFs 1GB each (Total = 2GB)\n");
 
         /* MA_LISA_MAP_i */
-        HW_WR_REG32(SOC_MA_MPU_CONF_REGS_BASE + LISA_MAP_0, 0x80700200U);
-        HW_WR_REG32(SOC_MA_MPU_CONF_REGS_BASE + LISA_MAP_1, 0xC0700100U);
+        HW_WR_REG32(SOC_MA_MPU_CONF_REGS_BASE + LISA_MAP_0, 0x80740300U);
+        HW_WR_REG32(SOC_MA_MPU_CONF_REGS_BASE + LISA_MAP_1, 0x80740300U);
         /* DMM_LISA_MAP_i */
-        HW_WR_REG32(SOC_DMM_CONF_REGS_BASE + LISA_MAP_0, 0x80700200U);
-        HW_WR_REG32(SOC_DMM_CONF_REGS_BASE + LISA_MAP_1, 0xC0700100U);
+        HW_WR_REG32(SOC_DMM_CONF_REGS_BASE + LISA_MAP_0, 0x80740300U);
+        HW_WR_REG32(SOC_DMM_CONF_REGS_BASE + LISA_MAP_1, 0x80740300U);
 
     }
 #endif
-- 
1.9.1

Fullscreen 0001-Modify-512MB-Bios-Memory-map-to-2GB-Bios-Memory-map.patch.txt Download

From 62df95bc772733b84a570ef3f6f1f4e71d84a4fe Mon Sep 17 00:00:00 2001
Date: Wed, 15 May 2019 10:15:42 +0530
Subject: [PATCH] Modify 512MB Bios Memory map to 2GB Bios Memory map
  Modify 512MB Bios Memory map to 2GB Bios Memory map
---
 apps/build/tda2px/mem_segment_definition_bios.xs               | 6 +++---
 apps/configs/tda2px_evm_bios_all/cfg.mk                        | 3 ++-
 links_fw/src/rtos/bios_app_common/tda2px/a15_0/a15_0.cfg       | 6 +++---
 links_fw/src/rtos/bios_app_common/tda2px/ipu1_0/Ammu1_bios.cfg | 2 +-
 links_fw/src/rtos/bios_app_common/tda2px/ipu2/Ammu2_bios.cfg   | 8 ++++----
 links_fw/src/rtos/links_ipu/system/system_bsp_init.c           | 4 ++--
 6 files changed, 15 insertions(+), 14 deletions(-)

diff --git a/apps/build/tda2px/mem_segment_definition_bios.xs b/apps/build/tda2px/mem_segment_definition_bios.xs
index 2c5fdd9..23ac426 100755
--- a/apps/build/tda2px/mem_segment_definition_bios.xs
+++ b/apps/build/tda2px/mem_segment_definition_bios.xs
@@ -18,7 +18,7 @@ function getMemSegmentDefinition_external(core)
     MB=KB*KB;
 
     DDR3_ADDR                   = 0x80000000;
-    DDR3_SIZE                   = 512*MB;
+    DDR3_SIZE                   = 2048*MB;
 
     /*
      * In case of ECC_FFI_INCLUDE, DDR3_BASE_ADDR_1 and DDR3_BASE_SIZE_1
@@ -27,7 +27,7 @@ function getMemSegmentDefinition_external(core)
      * If this DDR3_BASE_SIZE_0 is changed, update  Ipu1_0.cfg
      */
     DDR3_BASE_ADDR_0            = DDR3_ADDR;
-    DDR3_BASE_SIZE_0            = 508*MB;
+    DDR3_BASE_SIZE_0            = 1008*MB;
 
     /* The start address of the second mem section should be 16MB aligned.
      * This alignment is a must as a single 16MB mapping is used for EVE
@@ -42,7 +42,7 @@ function getMemSegmentDefinition_external(core)
          *  in non-cached virtual address of
          *  DDR3_BASE_ADDR_1 + 512*MB
          */
-        DDR3_BASE_ADDR_1        = DDR3_BASE_ADDR_1+512*MB;
+        /* DDR3_BASE_ADDR_1        = DDR3_BASE_ADDR_1+512*MB; */
     }
 
     DSP1_L2_SRAM_ADDR           = 0x40800000;
diff --git a/apps/configs/tda2px_evm_bios_all/cfg.mk b/apps/configs/tda2px_evm_bios_all/cfg.mk
index 77c430c..a3119b3 100755
--- a/apps/configs/tda2px_evm_bios_all/cfg.mk
+++ b/apps/configs/tda2px_evm_bios_all/cfg.mk
@@ -31,7 +31,8 @@ VSDK_BOARD_TYPE=TDA2PX_EVM
 DUAL_A15_SMP_BIOS=no
 
 # Supported values: DDR_MEM_512M
-DDR_MEM=DDR_MEM_512M
+DDR_MEM=DDR_MEM_1024M
+EMIFMODE=DUAL_EMIF_2X1GB
 
 # Supported values: ipu1_0 ipu1_1 a15_0 none
 NDK_PROC_TO_USE=a15_0
diff --git a/links_fw/src/rtos/bios_app_common/tda2px/a15_0/a15_0.cfg b/links_fw/src/rtos/bios_app_common/tda2px/a15_0/a15_0.cfg
index efa9900..7236a33 100755
--- a/links_fw/src/rtos/bios_app_common/tda2px/a15_0/a15_0.cfg
+++ b/links_fw/src/rtos/bios_app_common/tda2px/a15_0/a15_0.cfg
@@ -146,7 +146,7 @@ attrs1.shareable = 2;                      // sharerable
 attrs1.attrIndx = 2;                       // Cached, normal memory
 
 // Set the descriptor for each entry in the address range
-for (var i=0x80000000; i < 0xA0000000; i = i + 0x00200000) {
+for (var i=0x80000000; i < 0x9FFFFFFF; i = i + 0x00200000) {
     // Each 'BLOCK' descriptor entry spans a 2MB address range
     Mmu.setSecondLevelDescMeta(i, i, attrs1);
 }
@@ -160,9 +160,9 @@ attrs2.shareable = 2;                      // sharerable
 attrs2.attrIndx = 0;                       // Non-cache, normal memory
 
 // Set the descriptor for each entry in the address range
-for (var i=0xA0000000; i < 0xC0000000; i = i + 0x00200000) {
+for (var i=0xA0000000; i <= 0xBFFFFFFF; i = i + 0x00200000) {
     // Each 'BLOCK' descriptor entry spans a 2MB address range
-    Mmu.setSecondLevelDescMeta(i, i-0x20000000, attrs2);
+    Mmu.setSecondLevelDescMeta(i, i, attrs2);
 }
 
 // Region for NDK packet data buffers.
diff --git a/links_fw/src/rtos/bios_app_common/tda2px/ipu1_0/Ammu1_bios.cfg b/links_fw/src/rtos/bios_app_common/tda2px/ipu1_0/Ammu1_bios.cfg
index a9e30ed..a3a39fe 100755
--- a/links_fw/src/rtos/bios_app_common/tda2px/ipu1_0/Ammu1_bios.cfg
+++ b/links_fw/src/rtos/bios_app_common/tda2px/ipu1_0/Ammu1_bios.cfg
@@ -204,7 +204,7 @@ function init()
     entry.pageEnabled = AMMU.Enable_YES;
     entry.translationEnabled = AMMU.Enable_YES;
     entry.logicalAddress = 0xA0000000;
-    entry.translatedAddress = 0x80000000;
+    entry.translatedAddress = 0xA0000000;
     entry.size = AMMU.Large_512M;
     entry.L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
     entry.L1_posted = AMMU.PostedPolicy_NON_POSTED;
diff --git a/links_fw/src/rtos/bios_app_common/tda2px/ipu2/Ammu2_bios.cfg b/links_fw/src/rtos/bios_app_common/tda2px/ipu2/Ammu2_bios.cfg
index f7ca5f8..60aa355 100755
--- a/links_fw/src/rtos/bios_app_common/tda2px/ipu2/Ammu2_bios.cfg
+++ b/links_fw/src/rtos/bios_app_common/tda2px/ipu2/Ammu2_bios.cfg
@@ -204,13 +204,13 @@ function init()
     entry.pageEnabled = AMMU.Enable_YES;
     entry.translationEnabled = AMMU.Enable_YES;
     entry.logicalAddress = 0xA0000000;
-    entry.translatedAddress = 0x80000000;
+    entry.translatedAddress = 0xA0000000;
     entry.size = AMMU.Large_512M;
     entry.L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
     entry.L1_posted = AMMU.PostedPolicy_NON_POSTED;
     entry.L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
     entry.L2_posted = AMMU.PostedPolicy_NON_POSTED;
-/*
+
     var entry = AMMU.largePages[3];
     entry.pageEnabled = AMMU.Enable_YES;
     entry.translationEnabled = AMMU.Enable_YES;
@@ -221,5 +221,5 @@ function init()
     entry.L1_posted = AMMU.PostedPolicy_NON_POSTED;
     entry.L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
     entry.L2_posted = AMMU.PostedPolicy_NON_POSTED;
-*/
-}
\ No newline at end of file
+
+}
diff --git a/links_fw/src/rtos/links_ipu/system/system_bsp_init.c b/links_fw/src/rtos/links_ipu/system/system_bsp_init.c
index 0c05d90..c077f92 100644
--- a/links_fw/src/rtos/links_ipu/system/system_bsp_init.c
+++ b/links_fw/src/rtos/links_ipu/system/system_bsp_init.c
@@ -291,10 +291,10 @@ Int32 System_bspInit(void)
         vpsInitPrms.virtBaseAddr = 0x80000000U;
         vpsInitPrms.physBaseAddr = 0x80000000U;
 #else
-        vpsInitPrms.virtBaseAddr = 0xA0000000U;
+        vpsInitPrms.virtBaseAddr = 0x80000000U;
         vpsInitPrms.physBaseAddr = 0x80000000U;
         /* if Virtual address != Physical address then enable translation */
-        vpsInitPrms.isAddrTransReq = TRUE;
+        vpsInitPrms.isAddrTransReq = FALSE;
 #endif
         Vps_printf(" SYSTEM: VPDMA Descriptor Memory Address translation"
                     " ENABLED [0x%08x -> 0x%08x]\n",
-- 
1.9.1

Please let me know your valuable input .

Regards

Raj

0 Rishabh Garg over 6 years ago in reply to Raj Veer

TI__Guru 55685 points

Hi Raj,

LISA map change looks fine.
BIOS memory map changes needs to be tried to make sure that everything is working, looks ok at review.
Are you facing any issues?

Regards,
Rishabh

0 Raj Veer over 6 years ago in reply to Rishabh Garg

Intellectual 270 points

Hi Rishabh,

Thank you for support.

No , as of now ,I didn't observe any issue during basic testing.

we will test some more use cases on different core and let you know.

Regards
Raj

0 Rishabh Garg over 6 years ago in reply to Raj Veer

TI__Guru 55685 points

Hi Raj,

Ok. I am closing this thread.
Please mark appropriate posts as "This resolved my issue".

Regards,
Rishabh

0 Raj Veer over 6 years ago in reply to Rishabh Garg

Intellectual 270 points

Done

Processors

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RTOS/TDA2PXEVM: LISA and DMM EMIF register configuration for 2GB per EMIF (Tolal 4GB DDR3)