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AM3352: gpmc_ben0 when accessing 8bit device

shigehiro tsuda
Mastermind 9490 points

Part Number: AM3352

Hi,

The 8-bit device is connected to gpmc.
Refer to the following of the data sheet of AM335x as the timing of gpmc_ben0.
Figure 7-22. GPMC and NOR Flash—Asynchronous Read—Single Word

From this figure, it is always high when not accessing.
As a result of actually confirming the waveform, it seems to remain low (active).

What is the behavior of gpmc_ben0 at 8-bit access?
1. Keep high
2. Keep low
3. Low when accessed, high when not accessed.
4. Hold the previous logic when not accessing.

Best Regards,
Shigehiro Tsuda

  • 0
    TI__Mastermind 30601 points
    Hi Tsuda-san,

    Refer to 7.1.2.3.8.3.12 Byte Enable (BE1n/BE0n) of the TRM (SPRUH73)

    Byte enables are active low signals.

    Byte enable signals (BE1n/BE0n) are:
    • Valid (asserted or nonasserted according to the incoming system request) from access start to access completion for asynchronous and synchronous single accesses
    • Asserted low from access start to access completion for asynchronous and synchronous multiple read accesses
    • Valid (asserted or nonasserted, according to the incoming system request) synchronously to each written data for synchronous multiple write accesses

    =-=-=-
    Refer to this relevant thread... e2e.ti.com/.../442793

    BE0 and BE1 are "byte enables". They are low if data is transferred to a specific byte on the data bus.

    BE0 is active for a data transfer on D0...D7.
    BE1 is active for a data transfer on D8..D15.

    For 8 bit devices, all data is transferred on D0..D7.

    =-=-=-

    What data type do you use to access the GPMC? Uint16 *, Uint8 * ?

    Can you provide the register contents for the below registers, where n is the chip select you are using...

    GPMC_CONFIG
    GPMC_CONFIG1_n
    GPMC_CONFIG2_n
    GPMC_CONFIG3_n
    GPMC_CONFIG4_n
    GPMC_CONFIG5_n
    GPMC_CONFIG6_n
    GPMC_CONFIG7_n

    Regards,
    Mark
  • 0 in reply to Mark M
    Mastermind 9490 points

    Hi Mark,

    Thank you for quick reply.

    The data type is uint8 access, and the device connected to GPMC is accessed by LDRB and STR instruction in assembler.

    What is the operation specification of gpmc_ben0 at async non-mux 8 bit device setting?
    1. Is it high when not accessing with low only at the time of access?
    high-> low-> high
    2. When access is low, the status is maintained, so is it low when not accessing?
    low-> low-> low
    The GPMC_CONFIG1-7_n register is considered correct because the data can be read and written normally.

    Best Regards,
    Shigehiro Tsuda