RTOS/AM5726: sbl_main.c DSP init

Thanks Rahul

I followed the steps you wrote and generated the app file, it seems now that the SBL is entering the SBL_DSP1_BringUp function, however, it does not return from it. 

if (Entry.entryPoint_DSP1 != 0)
{
/* Release the DSP1 core out of reset */
UART_printf("DSP release...");
SBL_DSP1_BringUp(Entry.entryPoint_DSP1);
UART_printf("Done !\n");
}

Now i see "DSP release..." message but i don't see "Done !"

I Investigated a little bit and added comments to SBL_DSP1_BringUp function.

I found that it get stuck at the marked section

void SBL_DSP1_BringUp(uint32_t EntryPoint)
{
uint32_t i = 0U;

if(EntryPoint != 0U)
{
UART_printf("\nB4 SBL_DspEntryPointSet");
/* Set the Entry point of the application in the trampolene code. */
SBL_DspEntryPointSet(EntryPoint, dsp1Instruction);
UART_printf("\nAfter SBL_DspEntryPointSet");
/*
** Copy the dsp opcodes to create a trampoline at the specified memory
** location which is aligned at 0x400. This helps us in removing the
** entry address alignment limitation.
*/
memcpy((void *) DSP1_ENTRY_ADDR, (void *)dsp1Instruction,
sizeof(dsp1Instruction));
}

/*DSP L2RAM*/
/* Set the Entry point */
if (EntryPoint != 0U)
{
HW_WR_REG32(DSP1BOOTADDR, (DSP1_ENTRY_ADDR >> 0xAU));
}
else
{
HW_WR_REG32(DSP1BOOTADDR, (EntryPoint >> 0xAU));
/* Self branch loop for DSP */
for (i = 0; i < 8; i++) {
HWREG(CSL_MPU_DSP1_L2_SRAM_REGS + 4 * i) = 0x12;
}
}

/* Reset de-assertion for DSP CPUs */
UART_printf("\nReset de-assertion for DSP CPUs");
HW_WR_REG32((CSL_DSP_DSP1_PRM_REGS + RM_DSP1_RSTCTRL), 0x0);
/* Check the reset state: DSPSS Core, Cache and Slave interface */
UART_printf("\nCheck the reset state: DSPSS Core, Cache and Slave interface");
while ((HW_RD_REG32((CSL_DSP_DSP1_PRM_REGS + RM_DSP1_RSTST)) & 0x3) != 0x3);
/* Check module mode */
UART_printf("\nCheck module mode");
while ((HW_RD_REG32(CSL_MPU_DSP1_CM_CORE_AON_REGS + CSL_DSP1_CM_CORE_AON_CM_DSP1_DSP1_CLKCTRL_REG) & 0x30000) != 0x0);

}

Any ideas why ?

Maor

Ok.. I found that in my sbl_main.c the call for SBL_SlaveCorePrcmEnable() was commented out.
after i uncommented it, the boot got stuck.
digging into it i found that IPU1 is enabled, but all the rest are not.
I only kept IPU1 and DSP1 to be enabled for debug. I found that the call for DSP1_ClkEnable() is stuck, and when i dug there i found that the problem is in the SBL_PRCMModuleEnable at "check clock activity - ungated" section

void SBL_PRCMModuleEnable(uint32_t domainOffset,
uint32_t clkCtrlReg,
uint32_t clkStCtrlReg,
uint32_t clkActMask)
{
/* Enable the module */
UART_printf("\nEnable the module");
HW_WR_REG32(domainOffset + clkCtrlReg, PRCM_MODULEMODE_AUTO);
/* Check for module enable status */
UART_printf("\nCheck for module enable status");
while(PRCM_MODULEMODE_AUTO !=
(HW_RD_REG32(domainOffset + clkCtrlReg) & PRCM_MODULEMODE_MASK));

/* Check clock activity - ungated */
UART_printf("\nCheck clock activity - ungated ");
while(clkActMask != (HW_RD_REG32(domainOffset + clkStCtrlReg) & clkActMask));
}

any ideas ?

Hi Rahul 

Yes, i am working on a custom board.

I reviewed the files you specified and removed comments parts that were commented out and were relevant to the DSP (I compared the code with the standard code), however, when i built the MLO the compiler specified "nothing to do" and did not build a new MLO (i guess that these files are not included in the build)

However, i did manage to get the DSP to wake up by doing the following:

In DSP1_ClkEnable() function, the original order of the function is SBL_PRCMModuleEnable and then SBL_PRCMSetClkOperMode, when i reversed the order my problem was resolved and the DSP now wakes up after the MLO is finished.

Can you comment regarding what i have done ?

Thanks

Maor

Hi Rahul

The SBL_PRCMSetClkOperMode  is not being called in my board_clock.c file. Which CSL code is equivalent to it ?

Maor