Part Number: TMS320C6748
Other Parts Discussed in Thread: OMAPL138
Tool/software: Code Composer Studio
Greetings,
I've been working with the EDMA for sometime now with some success. Implementing the EDMA with the Cache has become a significant problem however particularly on the RX buffers of the EDMA.
Currently I've been using the CSLR Cache library which has worked well for significantly speeding up many routines when receiving data through the EDMA and have experienced no problem when receiving data via the EDMA and initializing the cache prior. When transitioning to the transmit routine, it seems as though despite my output buffers being correct, the EDMA is dropping sometimes hundreds of samples, and sometimes cutting data off at the end of the routine. It seems to be caused by the Cache routine and works fine when the cache is not enabled. However, the cache is necessary and I'd rather not write my own code that moves my necessary code back and fourth out of L2 and L1 memory and would rather use and already developed cache routine.
I've read through the cache user manual on the TMS320C674x processors about coherence with the EDMA. Although, more easily I feel as though it would be more ideal to place the output TX Buffers for the EDMA in a noncacheable portion of memory (Which I've tried by using Pragma statements but couldn't figure out how to change what level of SDRAM is Cachable)
Here is the code I use to initialize the Cache:
void disable_cache (void)
{
// Set DDR2 (MAR 192 - 223) as not cacheable
for(counter = 192; counter < 224; counter++)
CSL_FINST(cacheRegs->MAR[counter], CACHE_MAR_PC, NOT_CACHEABLE);
// Disable L1P
CSL_FINST(cacheRegs->L1PCFG, CACHE_L1PCFG_MODE, DISABLE);
stall = cacheRegs->L1PCFG;
// Disable L1D
CSL_FINST(cacheRegs->L1DCFG, CACHE_L1DCFG_MODE, DISABLE);
stall = cacheRegs->L1DCFG;
// Disable L2
CSL_FINST(cacheRegs->L2CFG, CACHE_L2CFG_MODE, DISABLE);
stall = cacheRegs->L2CFG;
}/* disable_cache */
void setup_DDR2_cache (void)
{
// Set SDRAM (MAR 192 - 223) as cacheable
for(counter = 192; counter < 224; counter++)
CSL_FINST(cacheRegs->MAR[counter], CACHE_MAR_PC, CACHEABLE);
}/* setup_SDRAM_cache */
void enable_L1 (void)
{
// Set L1P size to 32K
CSL_FINST(cacheRegs->L1PCFG, CACHE_L1PCFG_MODE, 32K);
stall = cacheRegs->L1PCFG;
// Set L1D size to 32K
CSL_FINST(cacheRegs->L1DCFG, CACHE_L1DCFG_MODE, 32K);
stall = cacheRegs->L1DCFG;
}/* enable_L1 */
void enable_L2 (void)
{
// Set L2 size to 256K
CSL_FINST(cacheRegs->L2CFG, CACHE_L2CFG_MODE, 128K);
stall = cacheRegs->L2CFG;
}/* enable_L2 */
Can someone tell me what is wrong with this cache routine or point me to one that is effective from some kind of TI software?
