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Original question:

TMS320C6748: How can I connect the MMC/SD controller to eMMC

TMS320C6748: Set the clock of SDMMC to 50M,caused the DATA CRC error.

user5948244
Prodigy 240 points
Part Number: TMS320C6748
Other Parts Discussed in Thread: CSD

Hi!

    When I set the clock of SDMMC to 50M,it will caused the data CRC error,when the clock is 25M,the data CRC is correct.

    The voltage of the SDMMC controller is 3.3V and the eMMC card is also support 3.3v,I have set the  HS_TIMING to high speed mode(52M) and check it by reading the ext. CSD register.

     The bus width is 8bit, How can I fix this issue? or we must change the voltage of SDMMC controller to 1.8V?

     Thanks!

 

    

  • 0
    TI__Mastermind 30120 points
    Hi!

    Did you encounter this issue on a custom board? Is there any way to reproduce it on a TI EVM?

    What is the core voltage? Recommend 1.2V or 1.3V

    The timing tables do not specify an IO voltage. I assume these timings are then valid for 1.8V and 3.3V, but I will confirm internally.
    - Table 6-40. Timing Requirements for MMC/SD
    - Table 6-41. Switching Characteristics for MMC/SD

    Are you using MMC0 or MMC1?

    Is it possible to slow the frequency down between 50MHz and 25MHz to see where the CRC errors begin to occur? Which CRC error bits are being set exactly?

    Could you take scope measurements of the signals with and without CRC errors?

    What sort of pull-resistors are present on the MMC/SD signals?

    I will ask internally about switching to 1.8V, but I do not see any description of this requirement in the datasheet or TRM.

    This thread is interesting (although for OMAP4):
    e2e.ti.com/.../340388

    I'll get back to you either tomorrow or next week.

    Regards,
    Mark
  • 0 in reply to Mark M
    Prodigy 240 points

    Hi Mark,

      Thanks for your response.

      Actually I use a curstomer board,the TI evm board do not support the emmc card,it is only support SD card with 4 bit data width,I need 8bit data width for eMMC.

    What is the core voltage? Recommend 1.2V or 1.3V

    The timing tables do not specify an IO voltage. I assume these timings are then valid for 1.8V and 3.3V, but I will confirm internally.

    - Table 6-40. Timing Requirements for MMC/SD
    - Table 6-41. Switching Characteristics for MMC/SD

    RP: the core voltage(DSP) is 1.2V and the I/O voltage is 3.3V for SDMMC controller.


    Are you using MMC0 or MMC1?

    RP: Use MMC1.

    Is it possible to slow the frequency down between 50MHz and 25MHz to see where the CRC errors begin to occur? Which CRC error bits are being set exactly?

    Could you take scope measurements of the signals with and without CRC errors? 

    RP: The function clock for the SDMMC is 100M,so I can divid 25M/33M/50M(max) for the Memory clock,I is also CRC error at 33M and 50M. I guess the waveform quality is poor when the speed is max than 25M,so it causd the CRC error,but I want to cofirm with TI team.

    What sort of pull-resistors are present on the MMC/SD signals? 

    RP: 10K. 

    Do you have some recommended schematic for the eMMC connection?

    I am looking forward to the furture response.

    Thanks again!

  • 0 in reply to Mark M
    Prodigy 240 points

    Hi Mark,

    Any news? thanks for your help.

  • 0 in reply to user5948244
    TI__Mastermind 30120 points
    Hi,

    Regarding setting HS_TIMING to high speed mode(52M), the spec reads...

    After the host verifies that the Device complies with version 4.0, or higher, of this standard, it has to enable the high speed mode timing in the Device, before changing the clock frequency to a frequency between 26MHz and 52MHz.

    The host uses the SWITCH command to write 0x01 to the HS_TIMING byte, in the Modes segment of the EXT_CSD register.

    Confirm you are completing these steps only, and are not trying to enter eMMC into HS200 mode (unsupported by C6748).

    =-=-

    Can you (re-)perform timing analysis of writes and reads?
    Writes: using output delay from C6748 switching characteristics, board trace lengths/ propagation delays, and the eMMC spec timing requirements.
    Reads: using output delay from eMMC spec, board trace lengths/ propagation delays, and the C6748 timing requirements.

    Based on some rough calculations, the eMMC device should be less than 5" of trace from the C6748 SDMMC pins. Recommend adding margin with shorter traces. Margin can be balanced for setup and hold time by altering the trace length of the CLK verses the data traces.
    How far away is the eMMC device from the processor?

    If you are able, probe the CLK vs data signals close to the eMMC during writes, and close to the C6748 during reads. Measure the setup and hold times against the rising edge of the clock. Data is launched on falling clock edge.

    =-=-

    10k pulls are in the range specified for eMMC
    CMD: 4.7k to 100k (@3.3V)
    DAT0-7: 10k to 100k (@3.3V)
    Include pull-ups on RST#, CMD, and all DAT signals. Usually there is not one on the clock, but designs like the AM335x Beagle Bone Black have it.
    github.com/.../BBB_SCH.pdf

    We highly recommend a 22-ohm series termination on the clock trace, close to the C6748 pins. This signal is used as an input on read transactions and the resistor will eliminate possible signal reflections on the signal which can cause false clock transitions (Pad loopback IO allows for easier-to-achieve setup time). You might be able to see the clock reflections with a high speed active probe, when probing very close to the C6748 pins.

    Hope this helps,
    Mark
  • 0 in reply to Mark M
    Prodigy 240 points
    Hi Mark,

    I will follow your suggestion and test it,thanks your help!