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Flashing Micron NAND 29F16G08DAA

Other Parts Discussed in Thread: TMS320DM6446

Hi,

I have been experiencing a large amount of trouble trying to program this chip, I then started searching around and found that other people are experiencing the same problems.  \

I have attached the post here that I had found.  Is there a way that I can get this to work?

Thanks in advance

 

POST INCLUDED BELOW:

 

http://linux.omap.com/pipermail/davinci-linux-open-source/2008-December/

009784.html

On Sun, 14 Dec 2008 19:54:04 -0800, David Brownell <david-b at pacbell.net>

wrote:

> On Sunday 14 December 2008, R. Simning wrote:

>> in chapter 11, section 11.1.1 (page 150), i have found that nand

>> devices supported allows a maximum page size of 2048 bytes.

>

> Supported by the ROM boot loader. I don't think there's any way the

> hardware is preventing a 4K page size ... it's all handled by

> software. You should be able to use that chip ... just not boot from

> it.

>

> (Unless TI can get you DM355 parts with an updated RBL.

> I could believe those are coming, given the two RBL+NAND issues listed

> in the errata document.)

>

>

>> Because this new nand device has a page size of 4096 bytes, and I

>> think this may be the problem I am having.

>

> One issue is that <linux/mtd/nand.h> defines

>

> /* This constant declares the max. oobsize / page, which

> * is supported now. If you add a chip with bigger oobsize/page

> * adjust this accordingly.

> */

> #define NAND_MAX_OOBSIZE 64

> #define NAND_MAX_PAGESIZE 2048

>

> So you'd need to change that to use a bigger page size.

That should probably come via the platform_data and passed down to struct nand_chip. Imagine a case with two chips in the board, one being 2k-pagesize and the other 4k-pagesize.

Don't even know if that would be possible, but someone might want to do something like that.

--

Best Regards,

Felipe Balbi

  • support for large block NAND devices has been added to RBL v 1.2; parts with this RBL version should be available already.

    You can check RBL version by reading address 0x9FFC

    ROM ID: 0x10040101 (Rev 1.1)ROM ID: 0x10040102 (Rev 1.2)

    Our documentation (e.g. ARM Subsystem Guide list NAND device compatible with RBL) will be updates soon, but in case you want to plan ahead, below is a list of supported big block NAND devices. 

      {0xF1,      0x99},    /* 128 MB - Big Block */
        {0xA1,      0x99},     /* 128 MB - Big Block */
        {0xAA,      0x9A},     /* 256 MB - Big Block */
        {0x2CDA,  0x9A},     /* Micron: MT29F2G08AAB, Size 256 MB - Big Block */
        {0xAC,      0x9A},    /* 512 MB - Big Block */
        {0x2CDC,  0x9A},     /* Micron: MT29F4G08BAB, MT29F8G08FAB Size 512 MB - Big Block */
        {0xB1,      0x99},     /* 128 MB - Big Block 0x22B1 */
        {0xC1,      0x99},     /* 128 MB - Big Block 0x22C1 */
        {0xADD3,  0x9A},    /* HYNIX: HY27UH08AG5M, HY27UH08AGDM 2 GB - Big Block 0x22D3 */
        {0xECD3,  0xDE},   /*SAMSUNG: 1 GB - Big Block MLC NAND */

    I hope this helps!

  • Correction.  large block NAND support will not be added until RBL 1.3 scheduled to be out in approximately 5 months.  Please disregard prior post.

  • Juan,

     

             Opened memory window in CCS and displayed location 0x9FFC to check for RBL version.

             Do not see ROM ID as you indicated

     

     

  • This is in DM355, correct?  I have not tried this myself, but I believe others have.  Are you using a GEL file to connect to DM355 via CCS? What do you see at this address?

  • Juan,

     

             This is for the DM6446.   Still working on getting the nandwriter working.

             Reading through posts regarding the RBL.   Want to confirm the RBL version on my

            TMS320DM6446 board and its compatibility with the Micron Big Block NAND we are using.

            (MT29F1G08ABBHC, which is listed as supported NAND).

             Also want to be able to dump IRAM after writing nandwriter to confiirm the UBL has been

            loaded properly.   Tried looking at locations 0x00000020 and did not see the magic number.

            In addition to that need to confirm that the ECC's are being written properly into the spare

           bytes region.   According to the documentation sprue14b   there are 4, 4 bytes ECCs at locations

           8h,18h,28h, and 38h.   All need to be initialized in big endian order.

            Have not verified that the nandwriter has initialized all four ECC's as required.

     

     

                                                                                                      Jerry

  • the '0x9FFC' listed above is for DM355 only; I do not belive there have been many changes to DM6446 RBL over the last year or two, but let me see if I can find a similar address for DM6446

  • Juan,

     

                 In addition to the RBL version display address,  I should be able to display the ubl contents

                in IRAM after running nandwriter at location 0x00000020?

                Nandwriter  is supposed to be loading ubl and u-boot.bin.

               Nandwriter shows that it completed successfully but  hyperterminal shows BOOTME.

               When I display 0x00000020 after running nandwriter(and before hyperterminal) I do not

               see the UBL signature displayed.

     

                                                                                                Jerry

     

  • Can you see the UBL in NAND using CCS?

  • Juan,

     

                    Run "nandwriter".   The output is listed below.

                    Also listed memory starting at 0x00000000.

     

                                                                           Jerry

     

    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF
    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF
    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF
    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF
    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF
    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF
    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF
    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF
    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF
    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF
    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF
    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF
    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF
    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF
    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF
    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF
    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF
    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF
    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF
    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF
    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF
    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF
    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF
    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF
    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF
    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF
    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF
    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF
    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF
    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF
    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF
    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF
    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF
    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF
    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF
    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF
    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF
    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF
    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF
    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF
    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF
    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF
    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0xFFFFFFFF    0x0A27B5BE    0x650BE2FC    0x19546C6E
    0xF63ED961    0x2AD48333    0x58861B1B    0x76C0C0A4    0xEECF5035    0xFDD116CD    0x4E219786
    0xD39C0D0B    0x51D08358    0x4B7C5D4D    0x57072BB1    0xAB6683AC    0xF35E2AF8    0x09A4DB1C
    0xF3E464A0    0xDAEE0471    0xD1DBF31D    0xB1789981    0xBE8C3707    0x68839E96    0x95865A7A
    0xFD62A306    0x57B173D2    0xB5B82896    0xC1F9794E    0xC7E3097C    0x0C002B60    0x9110BA4A
    0xCC0BD81B    0x75807ADC    0x46BC3C3F    0xC47A16E3    0xCE1FB76F    0x5696249A    0x64F84DF8
    0xEF0C2716    0xFF67C038    0xEE8CFA50    0xBF15123D    0x34930DA9    0x61C1F9DA    0x53566E9B
    0x2217A03A    0x2A44B572    0x0448574F    0x788C8472    0xBCB3EEDA    0xB5655DE8    0x24FC5E24
    0xAFECEC13    0x5E6C3AD6    0xD777639F    0x51A17510    0x8E891831    0x5A2103A0    0xCAB8A610
    0xE01DE301    0x68F8E964    0x6C9F4E56    0x14444BE6    0x2CC1D2D3    0x3F71EBD3    0x4244666A
    0xECFD06B0    0x296F5035    0x243BE084    0x1C841F60    0x7096F118    0x2E6077C5    0xEE911A83
    0x1BB0ED0B    0xF6EBDC57    0x6027A681    0x6498DA21    0x4922B2E9    0xD21EC614    0xD3C4A820
    0x37473F4D    0x701DE360    0xB6952964    0x37897AF5    0x472B1DD1    0xE11EC901    0xB3A42A47
    0xED57ACBB    0x5644E292    0x23991833    0x1E64FCDA    0x3E2F9417    0xB9B2284E    0x04B49A04
    0xB53E08AB    0xC4ACF577    0x57D18129    0x1B2080A8    0x05504022    0x3AEB823A    0x11BFB099
    0x7F746E0E    0xE1A63C62    0x93297412    0xF29AE6A4    0xA7A3A2D3    0xF780FD9B    0x9761D82E
    0x5756AEAC    0xA2787755    0x4C102207    0xA71BCBDA    0x5985BAA3    0x4BA413BD    0x9B9F1873
    0x9AF2E425    0xD5B2B5C0    0x89DB575A    0xC4EF2E08    0x1A6EA7F5    0x008834A1    0x1F1E6065
    0x115938A3    0x3630FC2F    0x88A3D2BF    0x0B496849    0xB0AB2A92    0xA4B03976    0x30C0EE61
    0x93D43CFB    0x96ECAFBE    0x54387322    0xAB0514B0    0x879970E6    0xB5734F83    0xDDDE82FB
    0xA5465D99    0xE7D6BA6A    0x9E08B9C9    0x8E3EC2D6    0xADCC52B3    0x86F5B84C    0xF8B72230
    0x06798362    0x8BE5E281    0xE8ECF009    0xA79F42F7    0x9224A0BE    0xD05B54F1    0xACA79ECC
    0x3C008218    0x07BA6D39    0x07F87198    0x3219D703    0x3BCBEC53    0x7E4CD15A    0xC4476913
    0x88F7FFF3    0x6752E366    0x0BE1C8E1    0xDACCE7E2    0xBED540CA    0x896BDE0C    0x5D4D38E8
    0x175E31C5    0x73AC3692    0xB72798D0    0xCF419E36    0x3F8F80E0    0x1CE46FF8    0xD679B20B
    0x1C33FFFE    0x6D655CB6    0xAF98664F    0xE8DE53F7    0x699BDFEE    0x0658476C    0x1E68BD3B
    0x7042D667    0xA55A9005    0xA3AC0972    0x339E03EB    0xDBB35047    0xA7255DB4    0x1E767557
    0x86A845CA    0x022EB536    0x3C891F4C    0x01838104    0x90D18C32    0xA4C6C0F0    0x041BCBCE
    0x7BA481BA    0x00D5FC70    0x78275463    0x427709FF    0x20E255BF    0xEDB081E4    0xECD3D32E
    0x66FE8E76    0x2F60C1A8    0x969691BB    0x57D26C36    0x92044F97    0x542C8BFB    0x474B68C1
    0x09D34F4F    0x8CCB2D5B    0x324BF272    0x0A20F37B    0xD73B00A3    0x17B1BC8F    0x9FE94424
    0xFAA85388    0x103094C4    0x16144B59    0xB971407C    0x82C6876E    0x34BB7791    0x438467E1

     

    Starting DM644x_NANDWriter.
    Enter the binary UBL file Name (enter 'none' to skip) :
    c:\tmp\ubl_davinci_nand.bin
    Number of blocks needed for header and data: 0x1
    Attempting to start write in block number 0x1.
    Unprotecting blocks 0x1 through 0x1.
    Erasing block 0x1 through 0x1.
    Writing header data to Block 0x1, Page 0x0
    Writing image data to Block 0x1, Page 0x1
    Writing image data to Block 0x1, Page 0x2
    Writing image data to Block 0x1, Page 0x3
    Writing image data to Block 0x1, Page 0x4
    Writing image data to Block 0x1, Page 0x5
    Writing image data to Block 0x1, Page 0x6
    Writing image data to Block 0x1, Page 0x7
    Protecting the entire NAND flash.
    Enter the U-boot or application file name (enter 'none' to skip):
    c:\tmp\u-boot.bin
    Enter the U-boot or application entry point (in hex):
    0x81080000
    Selected entry point is 0x81080000
    Enter the U-boot or application load address (in hex):
    0x81080000
    Number of blocks needed for header and data: 0x2
    Attempting to start write in block number 0x6.
    Unprotecting blocks 0x6 through 0x7.
    Erasing block 0x6 through 0x7.
    Writing header data to Block 0x6, Page 0x0
    Writing image data to Block 0x6, Page 0x1
    Writing image data to Block 0x6, Page 0x2
    Writing image data to Block 0x6, Page 0x3
    Writing image data to Block 0x6, Page 0x4
    Writing image data to Block 0x6, Page 0x5
    Writing image data to Block 0x6, Page 0x6
    Writing image data to Block 0x6, Page 0x7
    Writing image data to Block 0x6, Page 0x8
    Writing image data to Block 0x6, Page 0x9
    Writing image data to Block 0x6, Page 0xA
    Writing image data to Block 0x6, Page 0xB
    Writing image data to Block 0x6, Page 0xC
    Writing image data to Block 0x6, Page 0xD
    Writing image data to Block 0x6, Page 0xE
    Writing image data to Block 0x6, Page 0xF
    Writing image data to Block 0x6, Page 0x10
    Writing image data to Block 0x6, Page 0x11
    Writing image data to Block 0x6, Page 0x12
    Writing image data to Block 0x6, Page 0x13
    Writing image data to Block 0x6, Page 0x14
    Writing image data to Block 0x6, Page 0x15
    Writing image data to Block 0x6, Page 0x16
    Writing image data to Block 0x6, Page 0x17
    Writing image data to Block 0x6, Page 0x18
    Writing image data to Block 0x6, Page 0x19
    Writing image data to Block 0x6, Page 0x1A
    Writing image data to Block 0x6, Page 0x1B
    Writing image data to Block 0x6, Page 0x1C
    Writing image data to Block 0x6, Page 0x1D
    Writing image data to Block 0x6, Page 0x1E
    Writing image data to Block 0x6, Page 0x1F
    Writing image data to Block 0x6, Page 0x20
    Writing image data to Block 0x6, Page 0x21
    Writing image data to Block 0x6, Page 0x22
    Writing image data to Block 0x6, Page 0x23
    Writing image data to Block 0x6, Page 0x24
    Writing image data to Block 0x6, Page 0x25
    Writing image data to Block 0x6, Page 0x26
    Writing image data to Block 0x6, Page 0x27
    Writing image data to Block 0x6, Page 0x28
    Writing image data to Block 0x6, Page 0x29
    Writing image data to Block 0x6, Page 0x2A
    Writing image data to Block 0x6, Page 0x2B
    Writing image data to Block 0x6, Page 0x2C
    Writing image data to Block 0x6, Page 0x2D
    Writing image data to Block 0x6, Page 0x2E
    Writing image data to Block 0x6, Page 0x2F
    Writing image data to Block 0x6, Page 0x30
    Writing image data to Block 0x6, Page 0x31
    Writing image data to Block 0x6, Page 0x32
    Writing image data to Block 0x6, Page 0x33
    Writing image data to Block 0x6, Page 0x34
    Writing image data to Block 0x6, Page 0x35
    Writing image data to Block 0x6, Page 0x36
    Writing image data to Block 0x6, Page 0x37
    Writing image data to Block 0x6, Page 0x38
    Writing image data to Block 0x6, Page 0x39
    Writing image data to Block 0x6, Page 0x3A
    Writing image data to Block 0x6, Page 0x3B
    Writing image data to Block 0x6, Page 0x3C
    Writing image data to Block 0x6, Page 0x3D
    Writing image data to Block 0x6, Page 0x3E
    Writing image data to Block 0x6, Page 0x3F
    Writing image data to Block 0x7, Page 0x0
    Writing image data to Block 0x7, Page 0x1
    Writing image data to Block 0x7, Page 0x2
    Writing image data to Block 0x7, Page 0x3
    Writing image data to Block 0x7, Page 0x4
    Writing image data to Block 0x7, Page 0x5
    Writing image data to Block 0x7, Page 0x6
    Writing image data to Block 0x7, Page 0x7
    Writing image data to Block 0x7, Page 0x8
    Writing image data to Block 0x7, Page 0x9
    Writing image data to Block 0x7, Page 0xA
    Protecting the entire NAND flash.


    NAND boot preparation was successful!

  • Juan,

     

                 Our company  is considering replacing the existing big block nand with small block nand

                  given the problems we have been having with it.

                 We just upgraded to the MV 5.0 release and it looks like it works with the big block nand.

                  We have already modified DVFlasher and it works with BBN.

                 Seems like the industry is moving towards BBN.

                 Not sure if the nandwriter I am working on will work with any type of NAND right now.

     

                 Personnally think we should stick with BBN.   

                 Would like some feedback on this since we do not want to put anymore time into

                 getting BBN to work.

     

                                                                                                Jerry

  • Juan,

     

               Think this is possibly a DDR problem.

              Stepping through the code the DDR gets set to base addr 0x80000000.

              Memory allocation for hNandInfo is successful but "hNandInfo-flashBase"

             which is being set to 0x02000000 displays a garbage value. 

              Trying to figure out what could cause this.  Believe the gel file and the DDR2

             initialization is correct....

     

                                                                                         Jerry

  • Jerry,

    I do agree the industry is moving toward BBN devices, hence my recommendation would be to stick to BBN.  I am sure that Spectrum Digital which manufactures our DM6446 EVM will eventually run out of NAND parts inventory and may have to start building with BBN themselves; we typically write the software we provide for our EVMs, so if this happens, we will likely be upgrading much of the software to BBN.  Therefore, unless you can easily switch from SBN to BBN on your design in the future, I would recommend using BBN.

    what exactly are your running or stepping thru in CCS (UBL)?  I am not too familiar with CCS, but I am pretty certain that all DM6446 EVM GEL files I have come across setup the DDR2 correctly.

     

  • Juan,

              With the CCS you can't step through the GEL file.   It sets up the DDR2, EMIF etc.

              That is why in the nandwriter, these function calls are commented out.

               My DDR memory observations were bogus.  Was staring at this too much and needed a break.

               Since we are using the same ubl_davinci_nand.bin as used in the DVFlasher,  I assume the problem

               is in nandwriter. 

               Assume that the RBL rejects the load and reverts to UART mode(BOOTME) because of bogus UBL signature

              or nonmatching ECC's(page 132 sprue14b, page 132).   Can't check the ubl in NAND since CCS cannot display

             NAND memory.

              Going back and stepping through seeing if I can spot the cause.  Any suggestions, please let me know.

     

                                                                                                                                            Thanks, 

                                                                                                                                                                Jerry

  • Jerry,

    Thank you for the clarification, now things make a bit more sense to me.  I am not very experienced with CCS myself (more of a Linux guy) so maybe someone else can chime in and recommend something useful.

  • hello all,

    I'm looking for a driver for a micron nand flash ,the thing is , that I need the driver to be a NON -GPL .

    do you have one , or idea how to get non gpl drivers .probably this is not the last driver I need .

    I'm looking for : I2c driver to Smartflex. micron nand flash .usb host contl - how to define ULPI .

     

    thx,

    yuda