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66AK2H06: how to use SNOOP command?

YaoTing Mao
Intellectual 540 points

Part Number: 66AK2H06

Hi 

In the document,DSP CorePac User Guide, SPRUGW0C, chapter 4 level 2 memory and cache,  page 4-12,

it mentions we can keep cache coherence for L2 and L1D by SNOOP command:

SNPR (snoop read) and SNPW (snoop write) 

Does anyone how to use them?

Thanks,

  • 0
    TI__Guru**** 161600 points
    Hi,

    Additional details are given in the Cache User Guide. Have you checked section 2.4 Coherence in the document:
    www.ti.com/.../sprugy8.pdf

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    Intellectual 540 points
    Hi,
    in this document, page 36, it says:
    "
    C66x DSPs automatically maintain cache coherence for data accesses by the CORE and
    EDMA/IDMA through a hardware cache coherence protocol based on snoop
    commands. The coherence mechanism is activated on a DMA read and write access.
    When a DMA read of a cached L2 SRAM location occurs, the data is directly forwarded
    from L1D cache to the DMA without being updated in L2 SRAM. On a DMA write, the
    data is forwarded to L1D cache and is updated in L2 SRAM. "

    Does it mean i don't need to do configuration or program?
    The hardware does it automatically to me.
    e2e.ti.com/.../2959889
    Thanks,
  • 0 in reply to YaoTing Mao
    TI__Guru**** 161600 points
    Hi,

    That is what the Cache User Guide suggests. The sprugy8 document describes the cases where the programmer is responsible to maintain cache coherence:
    "In the following cases, it is your responsibility to maintain cache coherence:
    DMA or other external entity writes data or code to external memory that is then read by the CORE
    CORE writes data to external memory that is then read by DMA or another external entity
    DMA writes code to L2 SRAM that is then executed by the CORE (this case is supported by the hardware protocol on C621x/C671x and C64x DSPs, but is not supported on C66x DSPs)
    CORE writes code to L2 SRAM or external memory that is then executed by the CORE"

    I am not familiar in such details with the protocol, so I am looping the design team to elaborate.

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    Intellectual 540 points
    Hi Yordan,
    Thank you. please let me know how user can execute snoop command in C66x once you got answers.
    Regards,
    Yao-Ting
  • 0 in reply to Yordan Kovachev
    TI__Guru* 95265 points
    Hi,

    Please refer to this E2E: e2e.ti.com/.../255921

    I'd suggest the application maintain the cache coherency by using cache invalidate (E.G, EDMA writes something into a buffer, CPU needs to pick it up for processing) or cache invalidate and writeback (CPU writes something back into a buffer, for EDMA to pick up).

    Regards, Eric
  • 0 in reply to lding
    Intellectual 540 points
    Hi Eric,
    If i use those command, it will do all cache writeback and invalidate. right?
    The issue is I just want to writeback and invalidate the corresponding memory which changes by EDMA or peripheral devices.
    If i do action to the entire cache, CPU take a lot of resource or it may take a lot of time to re cache entire data.right?
    Regards,
    YaoTing
  • 0 in reply to YaoTing Mao
    TI__Guru* 95265 points
    Hi,

    When you cache invalidate or cache invalidate and writeback, it DOESN'T operate on the whole cache. The function has arguments of address pointer and length.

    See pdk_k2hk_4_0_13\packages\ti\drv\pcie\example\sample\src\pcie_sample.c
    Function:
    void cache_invalidate (void *ptr, int size)
    void cache_writeback (void *ptr, int size)

    Regards, Eric