I am trying to understand how to properly enable the WKUP_LFOSC0 crystal clock source.
The AM65x datasheet states that "WKUP_LFOSC0 crystal clock source is disabled until software configures the oscillator and should be enabled after PORz_OUT, MCU_PORz_OUT reset release."
The TRM also states "By default, WKUP_LFOSC0, and HFOSC1 are disabled, while WKUP_HFOSC0 is enable after PORz."
However, looking at the CTRLMMR_WKUP_LFOSC_CTRL register the GZ bit (bit 7) description states "oscillator disable. when GZ=1 the both bypass and oscillation mode are disabled". But it appears that this bit is set to "0" by default / at reset, which sounds like it means this clock would be enabled rather than disabled by default. Is this a typo or am I misunderstanding the description?
Is the GZ bit mentioned the only setting necessary to enable the WKUP_LFOSC0 clock? Our design directly uses a crystal rather than an external clock from an RTC like the EVM. How does this impact the software configuration? What needs to be implemented in software (if anything)?
Can you also provide more details regarding the RES_SEL and SW (oscillator gain adjustment) fields of the CTRLMMR_WKUP_LFOSC_CTRL register?