Tool/software: TI-RTOS
Hi.
My customers have questions on PCIe configuration registers.
Question 1:
About the following registers.
・PCIECTRL_EP_DBICS_PM_CAP [26] D2_SP
・PCIECTRL_EP_DBICS_PM_CAP [25] D1_SP
They looked at Figure 24-163. Do you agree with the following recognition?
Bit = 0 ::: It isn't possible to make state transition in D-state
Bit = 1 ::: It is possible to make state transition in D-state
Question 2:
What is the settings for the following register?
・PCIECTRL_PL_PHY_CTRL_R [31: 0] PHY_CTRL
Question 3:
What happens when you enable the following register?
We can't understand even if I looked at the register Description of TRM.
・PCIECTRL_PL_IATU_REG_CTRL_2[29]INVERT_MODE
Discription:Redefine match criteria as outside the defined range (instead of inside)
Regards,
Rei