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TCI6638K2K: Default C66x priority in MDMA register

Francois P
Expert 1050 points
Part Number: TCI6638K2K

Hello,

I would like to understand deeply how DDR3 controller manage commands priorities in the command FIFO. I red in the sprugw0c page 160 that MDMAARBU register who defines priority outside the C66x Corepac should be programmed to a higher priority but in reality, by default, the priority set is the lower value (0x7).

Here are screenshot from TI documentation relative to TCI6638K2K:

Does anyone can help me ?

Regards,

  • 0
    TI__Guru**** 161600 points
    Hi,

    I don't see the screenshot, but the User Guide states clearly that in most cases programmer should set a higher priority value:
    "The MDMAARBU register defines priority for MDMA transactions outside of the C66x CorePac. You may need to change its priority by programming the MDMAARBU register (as described in Section 8.3.5), depending on the system design. In most cases, MDMARBU should be programmed to a higher priority (lower value). "

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    Expert 1050 points

    Hi,

    Yes sorry, I just copied/pasted images but when I sent my question, they do not appeared. Anyway, your answer respound to my question.

    In my app, I used DDR3A on TCI6638K2K, in my understanding, when a command go outside the DSP, the command is manage by MSM controller first and then DDR3 controller. But the priority set in MDMAARBU stay the same until DDR3 memory controller ?


    For example, if I used SRIO who pass through TeraNet, then MSMC and at the end DDR3 memory controller, by default, the priority command is set at 0x4, if I set DSP CorePac priority at 0x3 for instance, does DSP command are set before SRIO command in the FIFO ?


    Regards,

  • 0 in reply to Francois P
    TI__Guru**** 161600 points
    Hi,

    Yes, my understanding is the same.

    Best Regards,
    Yordan