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RTOS/AM5718: EDMA issue on DSP

Markus Mueller
Expert 1370 points

Part Number: AM5718
Other Parts Discussed in Thread: SYSBIOS

Tool/software: TI-RTOS

Hi

I'm have written code on my AM5718 C66 DSP (Code Generator Tools V8.2) that configures the DMA to read SPI data and write it to internal OCMC memory.
So far this works.
When I change the destination address to be within L2SRAM (beginning at 0x0080'0000) I dont get data (memory location remains zero).
L2 cache size is 128kB, so 160kB is available for L2SRAM.
I'm using EDMA3 low level driver V2.12.5 (from pdk_am57xx_1_0_12).

Here is a code snipet:

// 1. Works
#pragma DATA_SECTION(AIO_ADCReceiveReg, "mem_section_within_ocmc_ram");

// 2. Does not work
//#pragma DATA_SECTION(AIO_ADCReceiveReg, "mem_section_within_l2sram");

uint32_t AIO_ADCReceiveReg[4] __attribute__ ((aligned (256)));

ExtADCRxParamSet.ACnt = 4;
ExtADCRxParamSet.BCnt = 4;
ExtADCRxParamSet.CCnt = 1;
ExtADCRxParamSet.BCntRld = 0;
ExtADCRxParamSet.Dst =  (uint32_t)&AIO_ADCReceiveReg[0].All;
ExtADCRxParamSet.DBIdx = sizeof(AIO_ADCReceiveReg[0]);
ExtADCRxParamSet.DCIdx = 0;
ExtADCRxParamSet.Src = SOC_MCSPI1_BASE + MCSPI_CHRX(AIO_ADC_SPI_CHANNEL);
ExtADCRxParamSet.SBIdx = 0;
ExtADCRxParamSet.SCIdx = 0;
ExtADCRxParamSet.Link = 0xFFFF;
Edma3Result = SYS_InitEdma3Channel(ExternalADCRxDataEvent, &ExtADCRxParamSet, EDMA3_DRV_SYNC_AB);

Snipet from map file:

MEMORY CONFIGURATION

         name            origin    length      used     unused   attr    fill
----------------------  --------  ---------  --------  --------  ----  --------
  L2SRAM                00800000   00028000  00002af0  00025510  RW X
  OCMC_RAM1             40340000   00020000  00002010  0001dff0  RW X
  SR_0                  40360000   00018000  00018000  00000000  RW X
  OCMC_DATA             4037c000   00003000  000024b8  00000b48  RW X
  DDR                   b0000000   0f000000  000c412a  0ef3bed6  RW X
  DDR_NO_CACHE          bf000000   01000000  00004010  00ffbff0  RW X

Case 1 (working):
40342000   AIO_ADCReceiveReg

Case 2 (not working);
00802c00   AIO_ADCReceiveReg

Any ideas why DMA does not work with L2SRAM destination?

Regards,
Markus

  • 0
    TI__Guru* 95265 points
    Hi,

    Maybe you write the data into DSP L2 memory via EDMA and L2 is not cache coherent. When you read from CPU (C66x core, or the CCS memory window), it just read from cache, not the physical memory so you got all zero? Try to do a cache invalidate before CPU read the data.

    Regards, Eric
  • 0 in reply to lding
    Expert 1370 points

    Hi Eric

    I'm already doing a cache invalidate like this:

    Cache_inv(AIO_ADCReceiveReg, sizeof(AIO_ADCReceiveReg), ti_sysbios_interfaces_ICache_Type_ALL, true);

    Otherwise It would not work from OCMC memory either. But with OCMC it works.

    Regards,
    Markus

  • 0 in reply to Markus Mueller
    TI__Guru* 95265 points
    Hi,

    Thanks for confirming that you did cache operation, then next what EDMA instance you used? From AM571x TRM,

    The SoC integrates the following EDMA instances:
    • One system-level EDMA
    • One DSP internal EDMA (per DSP)
    • One EVE internal EDMA (per EVE)

    There is no EVE on AM571x. Did you use the DSP internal DMA? From some of my work a few days ago, moving into L2 worked for me.
    If you use the system DMA, probably you need to convert L2 address into global address: like 0x10802c00 for DSP core 0, 0x11802c00 for DSP core 1.

    Also, check the alignment requirement below:

    16.2.4.3.2.2 Channel Source Address (SRC)
    The 32-bit source address parameter specifies the starting byte address of the source. For SAM in
    increment mode, there are no alignment restrictions imposed by EDMA. For SAM in constant addressing
    mode, it must program the source address to be aligned to a 256-bit aligned address (5 LSBs of address
    must be 0). If this rule is not observed, the EDMA_TPTC returns an error. Refer to Section 16.2.4.12.3
    Error Generation for additional details.
    16.2.4.3.2.3 Channel Destination Address (DST)
    The 32-bit destination address parameter specifies the starting byte address of the destination. For DAM
    in increment mode, there are no alignment restrictions imposed by EDMA. For DAM in constant
    addressing mode, it must program the destination address to be aligned to a 256-bit aligned address (5
    LSBs of address must be 0). If this rule is not observed, the EDMA_TPTC returns an error. Refer to
    Section 16.2.4.12.3 Error Generation for additional details.

    Regards, Eric
  • 0 in reply to lding
    Expert 1370 points

    Hi Eric

    Thank you for your detailed explanations.

    The EDMA3 low level driver that i'm using uses the system level EDMA.
    I'm using SAM and DAM in increment mode, so theres no limitation in alignment.

    I changed the destination address to have a 0x1000'0000 offset.
    Unfortunately it still does not work.

    I then checked the TRM (spruhz7h.pdf).
    In chapter 5.3.10.2 (DSP_EDMA View of the Address Space) on page 1676 there is a note in table 5-9 on
    memory range 0x1000'0000 to 0x10FF'FFFF saying:
    "The internal configuration space registers DSP_ICFG are visible ONLY to the C66x CPU (DSP_C0)
    within the DSP C66x CorePac , i.e. they are NOT visible to the DSP_EDMA "

    And in a further note on the same page:
    "With the DSP_MMU1 disabled, the subset of the memory map used for DSP_EDMA internal
    accesses will NOT be visible. Thus only addresse which equal 0x2000_0000 and above will
    be considered as valid 32-bit addresses ( i.e. L3_MAIN space accesses only) "

    Does this meen I have to enable the MMU or do I have no access at all to this memory range (containing L2 SRAM)?
    I already tried to enable the MMU in the .cfg file bit this resulted in program crash and no further debug access to the C66.

    Regrads,
    Markus

  • 0 in reply to Markus Mueller
    TI__Guru* 95265 points
    Hi,

    Thanks! We knew using system EDMA accessing OCMC worked. We knew also use DSP internal EDMA accessing DSP local L2 also worked. The question is if/how to use system-level EDMA to access DSP local L2 memory.

    This is a system interconnect issue and I asked our expert to comment.

    Regards, Eric
  • 0 in reply to lding
    TI__Mastermind 23125 points
    Marcus,
    I noticed you used 0x0080'0000 as your EDMA destination address. This address is actually the DSP view, while the EDMA sitting on the Main L3 interconnect. So you may want to try the memory map for L3_Main, where the DSP1 L2SRAM base address is 0x40800000.
    Please let us know if you still can not see the SPI data.
    regards
    jian
  • 0 in reply to jian35385
    Expert 1370 points

    Hi Jian

    You are absolutely right. Using the 0x4000'0000 Offset as EDMA destination address works.
    Interestingly there is not need to do a cache invalidate on these addresses. L1 data cache seems
    to be invalidated automatically after the EDMA has written to these addresses.

    Prior to posting this thread I had a look at a EDMA example where they used a function

    extern signed char*  getGlobalAddr(signed char* addr);

    before the adress got assigned to the EDMA source/destination adresses.
    When I also tried that aproach it failed. But I could not figure out where getGlobalAddr was defined and what it does.
    I included it as external and had no compilation error.
    Any Idea where this function is defined? Or even better: do you know an other function that works?

    Regards
    Markus