TMS320C5535: SPI not working

Hi Khyati,

What is the pinmux configuration in the EBSR register, PPMODE bit field?

For SPI_CS1 to be routed to the pins, you must choose PPMODE = MODE 1 or MODE 6.

Hope this helps,
Mark

Hi Mark,
Thanks for reply.
Yes, mode 1 is selected for PPMODE.
EBSR configuration is -
PPMODE - MODE1
SP1MODE - MODE2
SP0MODE - MODE2


Other system registers configuration are,-
CSL_FINS(sysRegs->PCGCR1, SYS_PCGCR1_SPICG, CSL_SYS_PCGCR1_SPICG_ACTIVE);

CSL_FINS(sysRegs->PSRCR, SYS_PSRCR_COUNT, 0x20);

CSL_FINS(sysRegs->PRCR, SYS_PRCR_PG4_RST, CSL_SYS_PRCR_PG4_RST_RST);

And SPI registers are,-
CSL_FINS(CSL_SPI_REGS->SPICMD2, SPI_SPICMD2_CSNUM, 0X01); //Chip Select 1 enable
//CSL_FINS(CSL_SPI_REGS->SPICCR, SPI_SPICCR_RST,1); //Clock Reset

CSL_FINS(CSL_SPI_REGS->SPICDR, SPI_SPICDR_CLKDV, 25 ); //Clock defined
CSL_FINS(CSL_SPI_REGS->SPIDCR1, SPI_SPIDCR1_CKPH1,1); //Data on rising edge and i/p on falling edge i.e. CKP1 = 0

CSL_FINS(CSL_SPI_REGS->SPICCR, SPI_SPICCR_CLKEN,1); //Clock Enable

//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~WP AND HLD DISABLE~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
CSL_GpioObj GpioObj;
CSL_GpioObj *hGpio1;// CSL_Status status;
hGpio1 = GPIO_open(&GpioObj, &status1);
// CSL_CPU_REGS->ST1_55 &= ~CSL_CPU_ST1_55_XF_MASK;//XF off
DSP_GPIO_setDirection (hGpio1, 12, GPIO_OUT);//HLD as output
status1 = GPIO_write(hGpio1, 12, 1); //HLD DISABLE
DSP_GPIO_setDirection (hGpio1,9, GPIO_OUT);//WP as output
status1 = GPIO_write(hGpio1, 9, 1); //WP DISABLE


Can you suggest something, what I am missing?

Hi Khyati,

Run a sanity check for me. Once the SPI transaction is executed (and you do not see a clock), halt the CPU and re-check the EBSR PPMODE bits.
I recall the SPI initialization might overwrite these bits for you.
Confirm all the bits are programmed as you expect.

And watch out for another peripheral reset inside the SPI_Init routine - it resets the PG4 group of peripherals again. You might want to comment that out.

Regards,
Mark

Hi Mark,
Thanks for quick reply.
I have checked EBSR after SPI init function which is showing as before i.e. its not changing after spi init.
Even all registers which is defined above are showing particular values.

Thanks,
Khyati

Hi Khyati,

Hmm I'm not sure what is going on.

Can you remove that pull-down on the SPI_CLK just to make sure it is not accidentally shorting to GND?
Do you ever see this pin toggle? Or any of the SPI pins for that matter? Does SPI_CS1 go low?

Are you following the initialization sequence in the TRM (spruh87) Section 8.2.12 Initialization and 8.3.3.1 Basic Initialization?

Can you try using the CSL SPI_Example after initializing the device with a GEL file? CSL: http://www.ti.com/tool/sprc133

What is in the status registers SPISTAT1 and SPISTAT2?

Do you have a TI EVM to reproduce this behavior with?

For debugging, you might try using SPI_CS0, or SPI_CS0 on the other SPI pins (EBSR PPMODE 3 or 5)...

What is the PLL configured to do? You might probe the SYSCLK at the CLKOUT pin after enabling it with the CLKOFF bit...

CPU ST3_55[0x0004@DATA]:
CLKOFF bit (bit 2) - The CLKOUT pin is enabled/disabled
When CLKOFF = 0, the CLKOUT pin is enabled; the associated clock signal appears on the pin.
When CLKOFF = 1, the CLKOUT pin is disabled.

Regards,
Mark

Are you following the initialization sequence in the TRM (spruh87) Section 8.2.12 Initialization and 8.3.3.1 Basic Initialization? 

Can you try using the CSL SPI_Example after initializing the device with a GEL file? CSL: http://www.ti.com/tool/sprc133

What is in the status registers SPISTAT1 and SPISTAT2?

Do you have a TI EVM to reproduce this behavior with?

For debugging, you might try using SPI_CS0, or SPI_CS0 on the other SPI pins (EBSR PPMODE 3 or 5)...

What is the PLL configured to do? You might probe the SYSCLK at the CLKOUT pin after enabling it with the CLKOFF bit...

CPU ST3_55[0x0004@DATA]: 
CLKOFF bit (bit 2) - The CLKOUT pin is enabled/disabled 
When CLKOFF = 0, the CLKOUT pin is enabled; the associated clock signal appears on the pin. 
When CLKOFF = 1, the CLKOUT pin is disabled.

Regards,
Mark

Hi Mark,

Thanks.

SPI_CLK pull down Resistor is mounted afterwards and even its not shorted to the ground.

SPI_CS1 is working fine.

CSL_SPI_Example is also used so I think Initialization process would be ok.

Thanks for suggestion of CLKOUT pin. On that pin, 100MHz clock is generating.

Here attached is DSP Hardware connection.Can you give feedback on it?

In last 1-2 days, there are some changes we have done in schematic, which are,-

- SPI_CLK of memory chip is pulled down to Ground via 100K and SPI_CS is pulled up to VCC via 10K.

- Removed  R36 and CLKOUT pin(100MHz) gives directly to the SPI_CLK. Will it work?

-After applying clock to memory from CLKOUT pin, write and read operations are not completed.

Thanks,

Khyati

SCHEMATIC DSP SPI.pdf

Hi Mark,

Thank you so much for your brief reply and finding issue of TX-RX pin.
I don't know, how SPI-TX/RX will be changed now.
I am trying to find out any solution. It's very difficult to connect on K1 and N4.
Meanwhile, I will check SPI_CLK during boot mode.
And revert back with feedback as soon as possible.

Thanks,
Khyati

Hi Mark,

Now, Hardware is changed according to your suggestion, i.e. MEM_DO and MEM_DI on N4 and K1.

CLKOUT is disconnected from SPI_CLK.

And During power up of the board, SPI_CLK is noticed and it gives some 7-8 pure clock pulses, but after that it disappears.

Kindly note that, registers values shown ok in debug mode.

I have tried above code which I have copied in previous text and another code from csl example, which is given below,-

Int16 status = CSL_TEST_FAILED;

Int16 result;
CSL_SpiHandle hSpi;
SPI_Config hwConfig;
volatile Uint32 looper;
volatile Uint16 value = 0;
Uint16 pageNo = 0x0000;
volatile Uint16 pollStatus;
volatile Uint16 delay;
volatile Uint16 fnCnt;

result = SEN_SPI_init();

if(CSL_SOK != result)
{
status = CSL_TEST_FAILED;
return (status);
}
else
{
printf ("SPI Instance Initialize successfully\n");
}

hSpi = SPI_open(SPI_CS_NUM_1, SPI_POLLING_MODE);

if(NULL == hSpi)
{
return (CSL_TEST_FAILED);
}
else
{
printf ("SPI Instance Opened successfully\n");
}

/** Set the hardware configuration */
hwConfig.spiClkDiv = SPI_CLK_DIV;
hwConfig.wLen = SPI_WORD_LENGTH_8;
hwConfig.frLen = SPI_FRAME_LENGTH;
hwConfig.wcEnable = SPI_WORD_IRQ_DISABLE;
hwConfig.fcEnable = SPI_FRAME_IRQ_DISABLE;
hwConfig.csNum = SPI_CS_NUM_1;
hwConfig.dataDelay = SPI_DATA_DLY_0;
hwConfig.csPol = SPI_CSP_ACTIVE_LOW;
hwConfig.clkPol = SPI_CLKP_LOW_AT_IDLE;
hwConfig.clkPh = SPI_CLK_PH_FALL_EDGE;

result = SPI_config(hSpi, &hwConfig);

if(CSL_SOK != result)
{
return (CSL_TEST_FAILED);
}
else
{
printf ("SPI Instance Configured successfully\n");
}

//******************************SPI-GPIO INIT***************************************************************

CSL_GpioObj GpioObj1;
CSL_GpioObj *hGpio1;// CSL_Status status;
hGpio1 = GPIO_open(&GpioObj1, &status);

CSL_CPU_REGS->ST1_55 &= ~CSL_CPU_ST1_55_XF_MASK;//XF off

DSP_GPIO_setDirection (hGpio1, 12, GPIO_OUT);//CLK as output
status = GPIO_write(hGpio1, 12, 1); //CLK off
DSP_GPIO_setDirection (hGpio1,9, GPIO_OUT);//WS as output
status = GPIO_write(hGpio1, 9, 1); //WS off
//******************************SPI-GPIO INIT***************************************************************

CSL_Status SEN_SPI_init(void)
{

volatile Uint16 delay;
ioport volatile CSL_SysRegs *sysRegs;

sysRegs = (CSL_SysRegs *)CSL_SYSCTRL_REGS;

CSL_FINS(sysRegs->PRCR, SYS_PRCR_PG4_RST, CSL_SYS_PRCR_PG4_RST_RST);//1

CSL_FINS(sysRegs->PCGCR1, SYS_PCGCR1_SPICG, CSL_SYS_PCGCR1_SPICG_ACTIVE);//2

/* Value of 'Reset Counter' */

CSL_FINS(sysRegs->PSRCR, SYS_PSRCR_COUNT, 0x20);

for(delay = 0; delay < 100; delay++);
CSL_FINS(sysRegs->EBSR, SYS_EBSR_PPMODE, CSL_SYS_EBSR_PPMODE_MODE1);

return(CSL_SOK);
}

Can you recognize the issue? Am I missing something in this or previous code?

Thanks,

Khyati

Hi Khyati,

Have you managed to make any progress with this issue?

Looking at the code you attached, I would recommend writing to PSRCR before writing to PRCR (and writing to PCGCR before PSRCR).

CSL_FINS(sysRegs->PRCR, SYS_PRCR_PG4_RST, CSL_SYS_PRCR_PG4_RST_RST);//1


CSL_FINS(sysRegs->PCGCR1, SYS_PCGCR1_SPICG, CSL_SYS_PCGCR1_SPICG_ACTIVE);//2

/* Value of 'Reset Counter' */

CSL_FINS(sysRegs->PSRCR, SYS_PSRCR_COUNT, 0x20);

The Peripheral Software Reset Counter Register (PSRCR) specifies the number of cycles to assert peripheral reset.

Writing to the Peripheral Reset Control Register (PRCR) (with a 1 in any bit field) initiates the peripheral reset for the number of cycle secified in PSRCR.

By writing to PRCR before PSRCR, the reset time period might be 0 cycles, not effectively resetting the peripheral(s) being reset.

Regards,
Mark

Hi Mark,

Sorry for late reply.

I was busy with some another testing.

Yes, now SPI is working file after changing that data lines K1 and N4.

We had tried to generate clock with PLL and then without PLL.

So, during data transmission, clock is visible and even read-write functions are also working fine.

Thank you very much for your kind support.

Thanks with Regards,

Khyati