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DM6467- Video Port DMA interrupts at lesser interval

Sathish
Intellectual 1950 points

Hi Champs,

One of the customer required below info, please help.

We are trying to analyze low latency systems and see what is the theoretical limit of DM6467 for the same. There are two major bottlenecks that we see in DM6467, Video Capture Port and Video Display Port. The Video port on DM6467 has an internal DMA that transfers the data to/from Video port to DDR memory buffer. From what we understand (Video port User guide) the interrupt indicating the buffer is filled (in case of Capture) and buffer is played out (in case of Display) occurs at every Frame or Field interval boundary. So in case of low latency systems this gives a major bottleneck.

We would like to know is there any way we can program the internal DMA to give interrupts at lesser interval for both Capture and Display.

We see capture path can provide line interrupts in case of RAW capture mode. But this mode is not suitable for systems which have Video Decoder that give output in either BT.656 or BT.1120 mode.

Thanks!!

Regards

Sathish

  • 0
    TI__Prodigy 650 points

    From a cursory look at the specification, I do not think DM6467T supports med field interrupts for standard modes like 1080p etc. For non-standard modes, one is free to set the linesize which can result in the interrupt at appropriate frame-ends, but probably that is not what you want.

    -Manju

  • 0
    TI__Mastermind 43875 points

    Sathish,

    The output data rate is asynchronous to the input so if you do not want to see 'tearing' in the output image then you can never have less than a single frame latency.

    Double buffering eliminates tearing but can introduce stuttering. Latency is always between 1 frame and 2 frames.

    Triple buffering eliminates both tearing and stuttering but can have between 1 frame and 3 frames of latency depending on the phase relationship and rates of the input and output video.

    If tearing is acceptable then you can point the capture input and the display output to the same frame buffer memory. In this case the latency will fluctuate between zero and a frame latency since the input and output are asynchronous to each other.

    BR,

    Steve

  • 0 in reply to Steve Clynes
    Prodigy 100 points

    Steve & Manju,

    Thanks for the replies.

    Steve,

    I understand that the Video Ports IN & Out are asynchronous and I agree to the fact of both of them point to same buffer memory there can be issues. What I would like to know is that can Video Capture Port give interrupt to system on data availability in less than field/frame boundary (for 720p or 1080p standard resolution in BT.1120 mode)?

    Regards,

    Ritesh

  • 0 in reply to Ritesh Parekh
    TI__Mastermind 43875 points

    Are you looking for an interrupt that occurs at a specific line number in the input video?

    The current interrupt occurs once the input buffer contains a complete image. Any interrupt occurring earlier will flag a buffer which is not complete, but it might have enough data there to start processing.

    Regardless though, if you want to reduce the input capture to output display delay then my previous analysis is still valid and the location of the interrupt does not have any effect on the range of delays you will find.

    If you are wanting to process the input video as soon as possible then generating an interrupt at some point in the input image (say, at a particular line) would help.

    As I say though, the issue cannot be eliminated if the source an destination are asynchronous and periodic.

    BR,

    Steve

  • 0 in reply to Steve Clynes
    Prodigy 220 points

    Hi,

    Sorry for "stupid" question.

    Who can get this interrupt - can DSP get such interrupt each 2-4 lines to start the processing?

    Is this relevant also for DM6446?

    Many thanks, Roman