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66AK2G12: 66AK2G12 POWER ON

Part Number: 66AK2G12
Other Parts Discussed in Thread: TLV62084

Hi 

As referenced to previous post link  "https://e2e.ti.com/support/processors/f/791/t/790414 "

Due to some debugging constraints i m not using "TPS65911" module for powering 66AK2G12 .CAN i power up device different core voltages  (e.g. 3.3V, 1.8V,1.35V, and CVDD 1.0V)  simultaneously by using  separate LDO's

Sir . NOW I found that in TI evaluation board for K2G_ICE (industrial communication engine) separate devices are used to power up SoC (66AK2G12) instead of single module. 

schematic diagram attached.P04_K2G_PowerSupply1.pdf

HOW in evaluation board control the  timing of power-up sequence described in device datasheet Section 5.9.1 .by using separate device for each core voltages...?

 

BEST REGARDS THANKS

  • Hi Jens,

    As I see the discrete components have power good signal that outputs once the output voltage reaches its nominal value.
    So the TLV62084 (3.3V Power Generation) gets enabled immediately when the power supply is plugged in (see the schematic, the 5.0V is input to 3.3V Power Generation ENABLE pin). Once the 3.3V output is stable the TLV62084 generates PGOOD_3V3 which serves as an ENABLE for the 1.8V supply and so on. You can also check Section 4.1 Power Distribution Diagram of the K2G ICE User Guide: www.ti.com/.../spruie3.pdf.

    Looping the design team to elaborate if needed.

    Best Regards,
    Yordan
  • Hi Yordan,

    Yes , i already evaluate this power good signal which  is used for sequential POWER ON of discrete components. But i want to confirm that " is this technique is  verified ?" because  power good signal timing is not  control-able. Its the default time of the devices  to power on next components.

    best regards 

  • Hi,

    Yes, using power good signal is verified (K2G ICE board) and complies with K2G power-up sequence.

    Best Regards,
    Yordan