AM5716: smc instruction

shigehiro tsuda

Mastermind 9490 points

Part Number: AM5716
Other Parts Discussed in Thread: SYSBIOS

Hi,

The following code is in 33.4 Services for HLOS Support of AM571x TRM.

SetL2CacheLatency FUNCTION
PUSH {R1-R12, LR}
LDR R12, =0x105
SMC 0x1
POP {R1-R12, PC}
ENDFUNC

When u-boot source is referenced, smc 0 is described as entering secure mode.
smc 0 @ SMC #0 to enter monitor mode

Which is correct?

Best Regards,
Shigehiro Tsuda

over 6 years ago

0 Krunal Bhargav34 over 6 years ago

TI__Mastermind 45015 points

Hello Shigehiro,

Based on my discussion with our experts, please use the u-boot source code as the reference. Also, I am wondering if you are experiencing any issues with the code?

Regards,
Krunal

0 shigehiro tsuda over 6 years ago in reply to Krunal Bhargav34

Mastermind 9490 points

Hi Krunal,

Thank you for quick reply.

I also checked the source of sysbios below, but it was like smc 0x1.
which one is correct?
bios_6_73_00_12\packages\ti\sysbios\family\arm\a15\Cache_asm_gnu.asm

SMP_ASM(ti_sysbios_family_arm_a15_smp_Cache_setL2AuxControlReg__I:)
UP_ASM(ti_sysbios_family_arm_a15_Cache_setL2AuxControlReg__I:)
push {r4-r12, lr}
ldr r12, =0x104
dsb
smc 0x1
pop {r4-r12, lr}

bx lr
.endfunc

Best Regards,
Shigehiro Tsuda

0 Brad Griffis over 6 years ago in reply to shigehiro tsuda

TI__Guru*** 125430 points

The number passed to SMC gets encoded as an immediate value in the opcode. It can optionally be leveraged by the corresponding secure handler. It's not used in this scenario, so both are correct.

0 shigehiro tsuda over 6 years ago in reply to Brad Griffis

Mastermind 9490 points

Hi Brad,

Thank you for quick reply.

By the explanation of your answer,I understand that both codes are correct.

It is an additional question.
The smc instruction causes a build error with the ti-cgt-arm_18.1.5.LTS compiler. In gcc it passes without build error.
Is it not supported by the ti-cgt-arm_18.1.5.LTS compiler?
If not supported, can secure mode be entered by the smi instruction?

Best Regards,
Shigehiro Tsuda

0 Krunal Bhargav34 over 6 years ago in reply to shigehiro tsuda

TI__Mastermind 45015 points

Hello Shigehiro,

The ti-cgt-arm_18.1.5.LTS compiler is only supported on M4 and for A15, TI supports GNU ARM Embedded v7-2018-q2.

Regards,
Krunal

0 shigehiro tsuda over 6 years ago in reply to Krunal Bhargav34

Mastermind 9490 points

Hi Krunal,

Thank you for quick reply.
I understand that A15 supports GNU compiler and ti-cgt-arm_18.1.5.LTS supports only M4.

Best Regards,
Shigehiro Tsuda

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AM5716: smc instruction