Hi,
I'd like to know the throughput of AM57xx GPMC which connects with FPGA.
According to the following E2E thread,
https://e2e.ti.com/support/processors/f/791/t/621859
it's about 1.15Gbps.
On the other hand, according to the following E2E thread,
https://e2e.ti.com/support/archive/internal/int_sitara_am335x/f/425/p/514604/1870281
it's about 15-20MBytes per second.
I think the difference between above values is quite large. Which one is the correct value?
Best regards,
HaTa.
Hi HaTa,
The explanation for the 1.15Gbps throughput assumes a 32-bit interface, but the GPMC only has a 16-bit interface.
I think the 5 cycles for address latch and latency is reasonable - it depends on the FPGA timings and latency. Recalculating with a 16-bit interface, I come up with 1.08 Gbps (135MB/s). 5+16 GPMC_CLK cycles to transfer 16x16 bits, GPMC_CLK = 88.6MHz.
There is no explanation for the 15-20MB/s figure, but perhaps it assumes asynchronous transfers, which are slower than synchronous.
It depends on the timings of the GPMC signals which are programmable through the GPMC_CONFIG registers. The GPMC signal timings need to satisfy the FPGA signal timing requirements.
I have observed throughput of 143MB/s with synchronous bursting GPMC transfers on the AM5728. This measurement was captured with the GPMC registers optimized for FPGA transactions. The DMA transferred 512 bytes to/from the GPMC. It will be slower if configured for non-synchronous or non-bursting transfers.
On AM572x, the GPMC_CLK is derived from the 266MHz GPMC_FCLK. Before being output from the GPMC_CLK pin, the 266MHz FCLK must be divided by 3 to satisfy the GPMC_CLK switching characteristics in the datasheet. This results in an 88.67MHz GPMC_CLK. The GPMC_CONFIG registers must be configured for this divided clock because the GPMC signal transitions are triggered by counters that increment with the 266MHz GPMC_FCLK.
The GPMC_FCLK on other devices like the AM335x and AM437x is 100MHz, and does not need to be divided before being output from the GPMC_CLK pin (for synchronous transfers). So theoretically, with a 100MHz GPMC_CLK the throughput can be higher with these devices.
Other timing constraints must be satisfied - see http://processors.wiki.ti.com/index.php/Tips_for_configuring_Sitara_GPMC_registers
See the below scope captures of a 512 byte DMA transfer to GPMC, configured for 16-word synch burst. The timings are very tight, and should be treated as a best case throughput.
Hope this helps,
Mark
