AM4376: Changing priority of interrupt

g.f.

From AM437x device side, Cortex-A9 interrupts are described in TRM:

- 3.3.1.3 Generalized Interrupt Controller (GIC)
- 8.1 ARM Cortex-A9 Interrupts

There are two interrupt priority related registers described in AM437x TRM: "Interrupt Priority Mask" at offset 0x004 and "Running Priority" at offset 0x014. The base addr of MPU_INTC is 0x48240100, see L4_PER memory map.

Regarding SW support of interrupt priority, could you please first clarify what SW you are planning to use? Do you use bare metal CCStudio project, or RTOS or Linux?

Regards,
Pavel

Hi pavel,

Thank you for the reply.

I understood that there are two interrupt priority related registers described in AM437x TRM.
But in "ARM Generic Interrupt Controller Architecture version2.0 Specification" it said as follow:

Interrupt Priority Mask Register (GICC_PMR)
- Purpose : Provides an interrupt priority filter. Only interrupts with higher priority than
the value in this register are signaled to the processor.

Running Priority Register(GICC_RPR)
- Purpose : Indicates the Running priority of the CPU interface.

It seems these two registers are not for setting each interrupt priority, am I wrong?

Actually this question is from my customer and they are planning to use Processor Linux SDK.

best regards,
g.f.

g.f. said:

Interrupt Priority Mask Register (GICC_PMR)
- Purpose : Provides an interrupt priority filter. Only interrupts with higher priority than
the value in this register are signaled to the processor.

Running Priority Register(GICC_RPR)
- Purpose : Indicates the Running priority of the CPU interface.

It seems these two registers are not for setting each interrupt priority, am I wrong?

This is ARM specific question and you should ask the ARM support team. What I can comment is that we have additional info in "ARM Generic Interrupt Controller Architecture Specification 1.0" and you can also check there.

I will also check how interrupt priority is handled in PSDK Linux and come back to you.

Regards,
Pavel

g.f.

Regarding u-boot, I can find only GICC_PMR (offset 0x04) is used:

u-boot-2018.01/arch/arm/include/asm/gic.h
u-boot-2018.01/arch/arm/cpu/armv7/nonsec_virt.S

Distributor priority register (ICD_IPTRn) seems to be in default state.

Regarding linux kernel, below are the interrupt priority related files:

linux-4.14.79/arch/arm/boot/dts/am4372.dtsi
linux-4.14.79/include/linux/irqchip/arm-gic.h
linux-4.14.79/drivers/irqchip/irq-gic.c
linux-4.14.79/drivers/irqchip/irq-gic-common.c


Regards,
Pavel

Hi Pavel,

Thank you for supporting me.

I found following source file in RTOS SDK which are setting interrupt priority.

- gic.c (location: pdk_am437x_1_0_14\packages\ti\starterware\soc)
There are following code in function InitGicDist():
***************************************************
/* Configure priority on all SPI interrupts to the lowest priority */
for (intrNum = 32; intrNum < maxValidIntr; intrNum += 4)
HW_WR_REG32((distBaseAddr + GIC_DIST_PRIORITY_REG_B(intrNum)),
GIC_CPU_INTF_MIN_PRI_ALL);
***************************************************

GIC_DIST_PRIORITY_REGB() was defined in gic_a9_mpcore_config.h as follow:
**********************************************************
#define GIC_DIST_PRIORITY_REG_B(REG) (0x0400 + REG)
#define GIC_DIST_PROC_TARGET_REG_B(REG) (0x0800 + REG)
**********************************************************

When setting the priority, it is accessing to the addess offset 0x400+REG.
As I mentioned above, "Interrupt Priority Register" are mapped to this offset address(0x400)
in "ARM Generic Interrupt Controller Architecture version2.0 Specification".
But in AM437x TRM page.163 "Table 3-7 DISTRIBUTOR REGISTERS",
"Interrupt Processor Target" are mapped to offset 0x400-0x4FC.
In ARM document, "Interrupt Processor Target" are mapped to offset 0x800-0x81C
which is same as gic_a9_mpcore_config.h .

So, I guess the range of 0x400-0x4FC in Table 3-7 of AM437x TRM should be
"Interrupt Priority Register" not "Interrupt Processor Target Register".
Could you please check either it is typo of AM437x TRM or not?

best regards,
g.f.

Hi Pavel,

Thank you for the reply.
I understood.

best regards,
g.f.