OMAP-L138: RTC split power

Hi Friedrich,

I'm looking into your questions. I'll get back to you within a day or two.

Below is all of the mentions to SPLITPOWER in the OMAP-L138 datasheet and TRM.

5.3 Recommended Operating Conditions
Note 1) The RTC provides an option for isolating the RTC_CVDD from the CVDD to reduce current leakage when the RTC is powered independently. If these power supplies are not isolated (CTRL.SPLITPOWER=0), RTC_CVDD must be equal to or greater than CVDD. If these power supplies are isolated (CTRL.SPLITPOWER=1), RTC_CVDD may be lower than CVDD.

28.2.3 Isolated Power Supply
The RTC has a power supply that is isolated from the rest of the system. This allows the RTC to continue to run while the rest of the system is not powered. In this state, the RTC time and calendar counters continue to run, but the powered down CPU is not able to receive RTC interrupts. Separate power supply pins for the RTC are provided on the device package.

28.2.3.1 Split-Power Circuitry
To decrease power consumption, RTC includes leakage-isolation circuitry that is activated by setting the SPLITPOWER bit in the control register (CTRL). Because of its isolated power supply, RTC does not have a power-on hardware reset signal. Therefore, upon initial device power-on, the RTC is in an unknown state until it has been properly configured. After the RTC module has been configured once, it functions as programmed as long as its power supply and clock source are provided.

28.2.3.2 Power Considerations
The RTC leakage-isolation circuitry requires that the CPU supply be powered down to VSS when the RTC is powered on while the rest of the device is powered off. A floating CPU supply creates undesired RTC leakage current. Also, the RTC power consumption is higher when the CPU is powered on versus the RTC power consumption when the CPU is powered off. Therefore, if the RTC module is expected to run from a small-capacity power supply (ex. watch battery) while the rest of the device is powered off, a power system should be implemented such that the RTC is powered from a high-capacity power supply when the CPU is powered on.

28.2.10 Reset Considerations
When the device is initially powered on, the RTC may issue spurious interrupt signals to the CPU. To avoid issues, a software reset should be performed on the RTC module before the CPU interrupt controller is initialized.
As the RTC is configured, the SPLITPOWER bit in the control register (CTRL) should be set.
A software reset is performed on the RTC by setting the SWRESET bit in the oscillator register (OSC). The software reset applies to all registers except the oscillator (OSC) and kick (KICKnR) registers. The RTC requires three 32.768-kHz reference clocks to pass before RTC registers can be accessed.

SPLITPOWER bit in CTRL Register
Enable leakage-isolation circuitry used for isolated power schemes. Write-only bit. Read-modify- write updates to the control register may unintentionally clear the SPLITPOWER bit because the bit always reads back 0.

Regards,
Mark

Hi Mark

Thanks for citing all the relevant sections from the datasheet. I already read them. Unfortunately this doesn't really answer my questions.

By the way: There is an additional question: How large is the power consumption of the RTC? I could not find any hint on this in the datasheet. Also, how large is the power consumption when the CPU is running, and how large is it when SPLITPOWER=1 ?

Thanks.

Hi Friedrich,

Regarding your last question, see the spreadsheet tool within the OMAP-L132/L138 Power Consumption Summary: www.ti.com/.../sprabg0

Regards,
Mark

Hi Friedrich

In addition to Mark's guidance, you may also read the usage note on RTC in the errata doc, that provides some more guidance on this.

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5.1.1 RTC Standby Power Consumption Is Elevated if the Module Is Not Configured Correctly

The RTC module is designed with the ability to keep time while the rest of the device is power cycled off

and on. This ability is achieved by placing the RTC in its own power domain and isolating it from the

device reset signal.

When the CVDD supply is powered down, the RTC_CVDD supply will experience elevated standby power

consumption because of leakage between the RTC and core power domains. The RTC module includes

circuitry that eliminates the leakage paths between the two domains when the SPLITPOWER bit is set to 1

in the control register (CTRL). The SPLITPOWER bit is a write-only bit that will always read back 0.

Therefore, typical read-modify-write sequences should not be used when writing to the CTRL register

because the SPLITPOWER bit will be cleared back to 0.

Also note that the SPLITPOWER bit has a default value of 0 after RTC module reset, and the only reset

available to the RTC module is a software reset, therefore RTC is in an indeterminate state when the

RTC_CVDD supply is first powered on. The RTC module should be reset, and the SPLITPOWER bit

should be set to 1 before placing the device in a CVDD powered down standby state.

The SPLITPOWER bit is permanently set to 1 inside the RTC module beginning with Silicon Revision 2.0

of the device.

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So the datasheet references for SPLITPOWER=0 is for silicon prior to rev 2.0. Which should be a don't care if you are on the latest rev of the silicon. 

Hopefully this clarifies your query on what does split power bit do and how to handle default being 0 etc.

Let us know if you have any further questions.
Regards

Mukul