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AM3358: Replacement DDR3 doesn't work without SW fix

Ed Billington
Prodigy 30 points

Part Number: AM3358

Hi,

We have a design with an AM3358 processor using an ISSI DDR3 memory (part number IS46TR16640A-125). This design has operated successfully for several years.

Due to memory obsolescence we have been investigating replacement parts. We have trialed an ISSI memory with internal ECC (part number IS46TR16640ED-15H). Although these are different speed grades, they are both compatible with our clock speed and memory configuration settings.

We initially found the new memory was not operating correctly. However, we have discovered that if we modify the SW to initiate a second memory initialization cycle (writing of the memories mode registers), the memory will perform perfectly. We have not changed any memory configuration settings.

We would like to understand why a second memory initialization cycle is required.

Thanks

Ed

  • 0
    TI__Guru* 95801 points
    Ed, how are you triggering the second write of the mode registers? Are you going through a full DDR initialization again?

    It may be possible that you are attempting to write to the memory too soon (maybe an issue with the DDR software initialization sequence), possibly something that the original memory could tolerate, but not the new one. What software did you originally start with, and did you change anything in the DDR init sequence.

    Can you also try to just reset your board (after power is stable), to see if the second mode register write isn't required? Just want to eliminate the possibility of any power up issues with supplies or VREF.

    Thanks,
    James
  • 0 in reply to JJD
    Prodigy 30 points
    James,

    We trigger the second write of the mode registers by writing a second time to the SDRAM Congig register. As described in section 7.3.3.6.2 of the Technical Reference Manual (SPRUH73P), "The EMIF also performs the initialization sequence whenever the SDRAM Config register is written".
    We have discovered that we need to wait for a minimum period of 21 us between the first and second SDRAM Config register write.

    In our initial testing we did not change any SW and therefore made no change to the DDR init sequence. It is important to us that the replacement of the obsolete memory does not requires any modification to out SW.

    We have tried many combinations of timing delays. This has been using both delays in the real time SW and break points using a debugger. We have not been able to achieve correct operation without introducing a second write to the SDRAM Config register.

    Our board has a watchdog. If the processor fails to start and service the watchdog, a processor reset is generated. In this way we have stable power and a continuously resetting processor.

    To try and isolate the root cause we are in the process of obtaining further alternative SDRAM parts to trial.

    Any further thoughts would be appreciated.

    Thanks for your response.

    Ed
  • 0 in reply to Ed Billington
    TI__Guru* 95801 points

    Hi Ed, what software are you using?  Can you send the source file(s) of the ddr configuration?

    Also, are you able to probe any DDR signals (DDR_CKE and/or DDR_RESET)?

    Regards,

    James

  • 0 in reply to JJD
    Prodigy 30 points

    James,

    We have now been able to try this design successfully with non-ECC memories. We believe the issue is due to some subtle difference with the ECC memory part. We are pursuing this with the memory manufacturer.

    Thanks for your help.

    Ed