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RTOS/AM5726: Shared memory configuration

Part Number: AM5726
Other Parts Discussed in Thread: SYSBIOS

Tool/software: TI-RTOS

Hi Everyone

I am working with AM5726 on a custom board.

Up until now I only worked with the A15 core. 

Currently i would like to assign shared memory between the DSP and the A15 in order to exchange data.

Can anyone recommend how ?

Thanks

Maor

  • Hello Maor,

    I recommend taking a look at the IPC module. IPC allows for exchanging messages and data between cores.

    Are you running Linux or TI-RTOS on the Arm core?

    There is a messageQ example which demonstrates sending and receiving messages between the Arm and DSP using the client/server pattern, where the Arm is the client and the DSP is the server. The maximize size of the message can be 512 bytes.

    If you need to send more than 512 bytes, I recommend referring to the big data ipc example. This example places buffers in shared memory and uses messageQ to share buffer information between cores.

    Details on the big data ipc example can be found here:

    For examples and training, please refer to the IPC sections of the Processor SDK Linux/RTOS SW Developer's Guides:

    Linux:

    TI-RTOS:

    For an introductory training video to IPC, please see the following.

    https://training.ti.com/intro-to-ipc-for-keystone-and-sitara?cu=519268

    If you have any questions please let me know.

  • Hi Sahin

    Thanks for the prompt reply.

    My arm is running TI-RTOS.

    For the meantime I managed to allocate some shared memory section using the app.cfg file for the arm and directly to the cmd file of the dsp.

    In the app.cfg I could also define this section as non cachable , howver, i still need to check how i can do it in the DSP since i am not using the app.cfg there.

    As for IPC, this is something i will need to utialize in the future for sure but for other purposes. 

    Thanks

    Maor

  • On the DSP, you can add a *.cfg file as well and then set the MAR bits like so,

    var Cache = xdc.useModule('ti.sysbios.family.c66.Cache');
    Cache.setMarMeta(BASE_ADDRESS, LENGTH, Cache.Mar_DISABLE);

    An example .cfg file can be found at ~\ipc_3_50_03_05\examples\AM572X_bios_elf\ex02_messageq\dsp1\Dsp1.cfg

  • Hi Sahin

    In the meantime it seems that the DSP uses the required memory segment as non cache. 

    However, i would like to understand, can i a cfg file to a non bios project ?

    Maor

  • Hi Maor,

    No, the .cfg file is used for SYSBIOS projects. Also, the IPC module does not support baremetal applications, only TI-RTOS. You mentioned using IPC in the future so I wanted to make sure you are aware of this. 

  • Thanks Sahin, good to know, i will keep this in mind.

    Since currently the DSP project was just to test the memory sharing with ARM it is a baremetal project. I will soon modify it to SYSBIOS project with TI-RTOS

    Thanks again for all the help :)

  • Happy to help :) please mark this thread as "Resolved" so we can close it out. Thanks!