RTOS/TDA3XEVM: How to change ddr from 512MB to 1024MB?

YiTing

Part Number: TDA3XEVM

Tool/software: TI-RTOS

I need to change the memory form 512MB to 1024MB,

Hardeware is ready for it,How can i change the setting? (mem_segment_definition_512mb.xs -> mem_segment_definition_1024mb.xs)

I used the ccs 8 version and the SDK is PROCESSOR_SDK_VISION_03_04_00_00,

Please provide more details.Thanks

over 5 years ago

0 Rishabh Garg over 5 years ago

TI__Guru 55685 points

Hi,

Can you see memory map guide: PROCESSOR_SDK_VISION_03_04_00_00\vision_sdk\docs\FeatureSpecificUserGuides\VisionSDK_UserGuide_MemoryMap.pdf

Regards,
Rishabh

0 YiTing over 5 years ago in reply to Rishabh Garg

Expert 1200 points

Thank for Reply

I have some question :

Step
1. I Change the Setting DDR_MEM variable in path : C:\PROCESSOR_SDK_VISION_03_04_00_00\vision_sdk\apps\configs\tda3xx_evm_bios_all\cfg.mk

2.cmd : gmake -s j6 apear warning

3.Try CS8 simulation but Can not work ( If do not change cfg.mk then working normally)

0 YiTing over 5 years ago in reply to Rishabh Garg

Expert 1200 points

below

0 Rishabh Garg over 5 years ago in reply to YiTing

TI__Guru 55685 points

Hi,

Did the compilation happen successfully.
Can you please share the log as a text file.

Regards,
Rishabh

0 YiTing over 5 years ago in reply to Rishabh Garg

Expert 1200 points

errorddr.log

 TDA3xx SBL Boot _zk190528_0

 Identified 15X15 Silicon 

 DPLL Configuration Completed 

 Clock Domain Configuration Completed 

 Module Enable Configuration Completed 

 TI EVM PAD Configuration Completed 

 DDR Configuration Completed 

 TDA3xx SOC Init Completed 

 App Image Download Begins 

 Manufacturer ID - 0x9d
 Device ID - 0x18
 IPU1 CPU0 Image Load Completed 

 IPU1 CPU1 Image Load Completed 

 DSP1 Image Load Completed 

 App Image Download Completed 

 EVE MMU configuration completed 

*****************************************************************

 32K Timer is used to measure cycles, divide by 32K to get time in seconds 

 Reset to SBL Init Cycles - 342  (10.43 ms) 

 SBL Initial Config Cycles - 210  (6.40 ms) 

 SOC Init Cycles - 469  (14.31 ms) 

 DDR Config Clock Cycles - 228  (6.95 ms) 

 App Image Load Cycles - 6610  (201.72 ms) 

 Slave Core Bootup Cycles - 112  (3.41 ms) 

 SBL Boot-up Cycles - 7631  (232.87 ms) 

 Time at which SBL started IPU1_0 - 7973  (243.31 ms) 

*****************************************************************

 Jumping to IPU1 CPU1 App 

 Jumping to IPU1 CPU0 App

hi gmake -s j6 successfully but can not work

0 Rishabh Garg over 5 years ago in reply to YiTing

TI__Guru 55685 points

Hi,

Did you change AMMU for M4 and MMU for A15 to map 0xA000_0000 virtual address to 0xA000_0000 physical address instead of 0x8000_0000 physical address.

Regards,
Rishabh

0 YiTing over 5 years ago in reply to Rishabh Garg

Expert 1200 points

The AMMU file for M4 , I think is change AMMU virtual address physical address.2046.Ammu1_bios.cfg

    if (platformMem == "DDR_MEM_1024M")
    {
        entry.logicalAddress = 0xA0000000;
        entry.translatedAddress = 0xA0000000;
    }
    else
    {
        entry.logicalAddress = 0xA0000000;
        entry.translatedAddress = 0x80000000;
    }

0 Rishabh Garg over 5 years ago in reply to YiTing

TI__Guru 55685 points

Hi,

I think you have not added below in config_<cpu>.bld files present here: PROCESSOR_SDK_VISION_03_06_00_00\vision_sdk\build\rtos\tda3xx\

if (platformMem == "DDR_MEM_1024M")
{
  var MemSegDefine = xdc.loadCapsule("" + appPath + "/build/tda3xx/mem_segment_definition_512mb.xs");
}

Regards,

Rishabh

0 YiTing over 5 years ago in reply to Rishabh Garg

Expert 1200 points

HI the file is already set

if (platformMem == "DDR_MEM_1024M")
{
  var MemSegDefine = xdc.loadCapsule("" + appPath + "/build/tda3xx/mem_segment_definition_1024mb.xs");
}

if (platformMem == "DDR_MEM_512M")
{
  var MemSegDefine = xdc.loadCapsule("" + appPath + "/build/tda3xx/mem_segment_definition_512mb.xs");
}

if (platformMem == "DDR_MEM_128M")
{
  var MemSegDefine = xdc.loadCapsule("" + appPath + "/build/tda3xx/mem_segment_definition_128mb.xs");
}

0 Rishabh Garg over 5 years ago in reply to YiTing

TI__Guru 55685 points

Hi,

Can you share the updated mem_segment_definition_1024mb.xs.

Regards,

Rishabh

0 YiTing over 5 years ago in reply to Rishabh Garg

Expert 1200 points

mem_segment_definition_1024mb.txt

/*
 *******************************************************************************
 *
 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
 * ALL RIGHTS RESERVED
 *
 *******************************************************************************
 */

/*
 *  ======== mem_segment_definition.xs ========
 *  ======== Single file for the memory map configuration of all cores =========
 */

function getMemSegmentDefinition_external(core)
{
    KB=1024;
    MB=KB*KB;

    DDR3_ADDR                   = 0x80000000;
    DDR3_SIZE                   = 1024*MB;

    DDR3_BASE_ADDR_0            = DDR3_ADDR;
    DDR3_BASE_SIZE_0            = 512*MB;


    if(java.lang.System.getenv("OPENVX_INCLUDE")=="yes")
    {
        OPENVX_SHM_SIZE         = 2*MB;
        DDR3_BASE_SIZE_0        = DDR3_BASE_SIZE_0 - OPENVX_SHM_SIZE;
    }


    /* The start address of the second mem section should be 16MB aligned.
     * This alignment is a must as a single 16MB mapping is used for EVE
     * to map SR0, REMOTE_LOG_MEM sections.
     * tlb_config_eveX.c need to be modified otherwise
     */
    DDR3_BASE_ADDR_1            = DDR3_BASE_ADDR_0 + 512*MB;
    DDR3_BASE_SIZE_1            = 512*MB;
    if(core=="ipu1_1" || core=="ipu1_0")
    {
        /*  for ipu1_0, ipu1_1, DDR3_BASE_ADDR_1 should be
         *  in non-cached virtual address of
         *  DDR3_BASE_ADDR_1 + 512*MB
         */
        /*DDR3_BASE_ADDR_1        = DDR3_BASE_ADDR_1+512*MB;*/
    }

    OCMC1_ADDR                  = 0x40300000;
    OCMC1_SIZE                  = 512*KB;

    DSP1_L2_SRAM_ADDR           = 0x40800000;
    DSP1_L2_SRAM_SIZE           = 288*KB;

    DSP2_L2_SRAM_ADDR           = 0x41000000;
    DSP2_L2_SRAM_SIZE           = 288*KB;

    EVE1_SRAM_ADDR              = 0x42000000;
    EVE1_SRAM_SIZE              = 1*MB;

    TOTAL_MEM_SIZE              = (DDR3_SIZE);

    /* First 512 MB - cached */
    /* EVE vecs space should be align with 16MB boundary, and if possible try to fit
     * the entire vecs+code+data in 16MB section. In this case a single TLB map would
     * be enough to map vecs+code+data of an EVE.
     * tlb_config_eveX.c need to be modified if any of these EVE memory sections or
     * SR1_FRAME_BUFFER_MEM section is modified.
     */

    /* EVE self-branch instruction block - EVE1_VECS
     * In SBL, EVE self-branch instruction is inserted @ 0x80000000 if no AppImage for EVE.
     * This could overwrites the code/data loaded at 0x80000000.
     * So Reserving a small memory block in the beginning of the DDR @0x8000 0000 for
     * EVE self-branch instruction if no AppImage for EVE.
     * If EVE enabled, then the EVE VECS/DATA/CODE is placed @0x8000 0000,
     * and hence we did not observe any issue.
     * If EVE is disabled, then also DO NOT remove this EVE1_VECS section @0x80000000,
     * if no AppImage for EVE. This could overwrites the code/data loaded at 0x80000000
     */

    EVE1_VECS_SIZE              = 0.5*MB;
    EVE1_CODE_SIZE              =   2*MB;
    EVE1_DATA_SIZE              =13.5*MB;
    NDK_DATA_SIZE               =   4*MB;
    IPU1_1_CODE_SIZE            =   2*MB;
    IPU1_1_DATA_SIZE            =  10*MB;
    IPU1_0_CODE_SIZE            =  10*MB;
    IPU1_0_DATA_SIZE            =  13*MB;
    DSP1_CODE_SIZE              =   2*MB;
    DSP1_DATA_SIZE              =  13*MB;
    DSP1_DATA_SIZE_2            =   1*MB;
    DSP2_CODE_SIZE              =   2*MB;
    DSP2_DATA_SIZE              =  13*MB;
    DSP2_DATA_SIZE_2            =   1*MB;
    if(java.lang.System.getenv("ECC_FFI_INCLUDE")=="yes")
    {
        /* Ensure ECC regions are 64kB aligned */
        SR1_BUFF_ECC_ASIL_SIZE      =   1*MB;
        SR1_BUFF_ECC_QM_SIZE        =  40*MB;
        SR1_BUFF_NON_ECC_ASIL_SIZE  =   1*MB;
    }
    else
    {
        SR1_BUFF_ECC_ASIL_SIZE      =   4*KB;
        SR1_BUFF_ECC_QM_SIZE        =   4*KB;
        SR1_BUFF_NON_ECC_ASIL_SIZE  =   4*KB;
    }

    /*  memory is       512MB   */
    /*  NDK_DATA_SIZE     4MB   */
    /*  IPU1_1_CODE_SIZE  2MB   */
    /*  IPU1_1_DATA_SIZE 10MB   */
    /*  IPU1_0_CODE_SIZE 10MB   */
    /*  IPU1_0_DATA_SIZE 13MB   */
    /*                          */

    SR1_FRAME_BUFFER_SIZE       = 472*MB - (SR1_BUFF_ECC_ASIL_SIZE + SR1_BUFF_ECC_QM_SIZE + SR1_BUFF_NON_ECC_ASIL_SIZE);

    /* Second 512 MB - non-cached */
    /* The start address of the second mem section should be 16MB aligned.
     * This alignment is a must as a single 16MB mapping is used for EVE
     * to map SR0, REMOTE_LOG_MEM sections.
     * tlb_config_eveX.c need to be modified otherwise
     */
    /* FFI needs start address of all sections to be 4 KB aligned. */
    REMOTE_LOG_SIZE             =  160*KB;
    SYSTEM_IPC_SHM_SIZE         =  480*KB;
    LINK_STATS_SIZE             =  256*KB;
    HDVPSS_DESC_SIZE            =  256*KB;
    SR0_SIZE                    =  2*MB;

    /* Cached Section */
    /* EVE vecs space should be align with 16MB boundary, and if possible try to fit
     * the entire vecs+code+data in 16MB section. In this case a single TLB map would
     * be enough to map vecs+code+data of an EVE.
     * tlb_config_eveX.c need to be modified if any of these EVE memory sections or
     * SR1_FRAME_BUFFER_MEM section is modified.
     */

    /* EVE self-branch instruction block - EVE1_VECS
     * In SBL, EVE self-branch instruction is inserted @ 0x80000000 if no AppImage for EVE.
     * This could overwrites the code/data loaded at 0x80000000.
     * So Reserving a small memory block in the beginning of the DDR @0x8000 0000 for
     * EVE self-branch instruction if no AppImage for EVE.
     * If EVE enabled, then the EVE VECS/DATA/CODE is placed @0x8000 0000,
     * and hence we did not observe any issue.
     * If EVE is disabled, then also DO NOT remove this EVE1_VECS section @0x80000000,
     * if no AppImage for EVE. This could overwrites the code/data loaded at 0x80000000
     */

    /* Changes for ECC
     * EVE code will run only from non-ECC region
     * All code section should be next to non-ECC region (using EVE section) to
     * allow them to be easily taken out of ECC region for debugging.
     * Make sure DSP1_DATA_ADDR_2 and DSP2_DATA_ADDR_2 are immediately after
     * SR1_BUFF_ECC_QM_ADDR and don't exceed 2*MB in total - this size should
     * be kept constant across all platforms and should match the increment
     * to heapStats.heapSize in utils_xmc_mpu.c
     */
    NDK_DATA_ADDR              = DDR3_BASE_ADDR_0;
    IPU1_1_CODE_ADDR           = NDK_DATA_ADDR              + NDK_DATA_SIZE;
    IPU1_0_CODE_ADDR           = IPU1_1_CODE_ADDR           + IPU1_1_CODE_SIZE;
    IPU1_1_DATA_ADDR           = IPU1_0_CODE_ADDR           + IPU1_0_CODE_SIZE;
    IPU1_0_DATA_ADDR           = IPU1_1_DATA_ADDR           + IPU1_1_DATA_SIZE;
    SR1_BUFF_ECC_ASIL_ADDR     = IPU1_0_DATA_ADDR           + IPU1_0_DATA_SIZE;
    SR1_BUFF_ECC_QM_ADDR       = SR1_BUFF_ECC_ASIL_ADDR     + SR1_BUFF_ECC_ASIL_SIZE;
    SR1_BUFF_NON_ECC_ASIL_ADDR = SR1_BUFF_ECC_QM_ADDR       + SR1_BUFF_ECC_QM_SIZE;
    SR1_FRAME_BUFFER_ADDR      = SR1_BUFF_NON_ECC_ASIL_ADDR + SR1_BUFF_NON_ECC_ASIL_SIZE;

    /* Non Cached Section */
    /* The start address of the second mem section should be 16MB aligned.
     * This alignment is a must as a single 16MB mapping is used for EVE
     * to map SR0, REMOTE_LOG_MEM sections.
     * tlb_config_eveX.c need to be modified otherwise
     */
    SR0_ADDR                   = DDR3_BASE_ADDR_1;
    REMOTE_LOG_ADDR            = SR0_ADDR              + SR0_SIZE;
    LINK_STATS_ADDR            = REMOTE_LOG_ADDR       + REMOTE_LOG_SIZE;
    SYSTEM_IPC_SHM_ADDR        = LINK_STATS_ADDR       + LINK_STATS_SIZE;
    HDVPSS_DESC_ADDR           = SYSTEM_IPC_SHM_ADDR   + SYSTEM_IPC_SHM_SIZE;
    OPENVX_SHM_ADDR            = HDVPSS_DESC_ADDR      + HDVPSS_DESC_SIZE;

    EVE1_VECS_ADDR             = DDR3_BASE_ADDR_1           + 16*MB;
    EVE1_CODE_ADDR             = EVE1_VECS_ADDR             + EVE1_VECS_SIZE;
    EVE1_DATA_ADDR             = EVE1_CODE_ADDR             + EVE1_CODE_SIZE;
    DSP1_CODE_ADDR             = EVE1_DATA_ADDR             + EVE1_DATA_SIZE;
    DSP2_CODE_ADDR             = DSP1_CODE_ADDR             + DSP1_CODE_SIZE;
    DSP1_DATA_ADDR             = DSP2_CODE_ADDR             + DSP2_CODE_SIZE;
    DSP2_DATA_ADDR             = DSP1_DATA_ADDR             + DSP1_DATA_SIZE;
    DSP1_DATA_ADDR_2           = DSP2_DATA_ADDR             + DSP2_DATA_SIZE;
    DSP2_DATA_ADDR_2           = DSP1_DATA_ADDR_2           + DSP1_DATA_SIZE_2;

    if ((SR1_FRAME_BUFFER_ADDR + SR1_FRAME_BUFFER_SIZE) > (DDR3_BASE_ADDR_0 + DDR3_BASE_SIZE_0))
    {
      throw xdc.$$XDCException("MEMORY_MAP OVERFLOW ERROR ",
                               "\nRegion End: " + "0x" + java.lang.Long.toHexString(DDR3_BASE_ADDR_0 + DDR3_BASE_SIZE_0) +
                               "\nActual End: " + "0x" + java.lang.Long.toHexString(SR1_FRAME_BUFFER_ADDR + SR1_FRAME_BUFFER_SIZE));
    }
/*
    if(java.lang.System.getenv("OPENVX_INCLUDE")=="yes")
    {
        if ((OPENVX_SHM_ADDR + OPENVX_SHM_SIZE) > (EVE1_VECS_ADDR))
        {
            throw xdc.$$XDCException("MEMORY_MAP OVERFLOW ERROR ",
                               "\nRegion End: " + "0x" + java.lang.Long.toHexString(DDR3_BASE_ADDR_1 + DDR3_BASE_SIZE_1) +
                               "\nActual End: " + "0x" + java.lang.Long.toHexString(OPENVX_SHM_ADDR + OPENVX_SHM_SIZE));
        }
    }
    else
    {
        if ((DSP2_DATA_MEM_2_ADDR + DSP2_DATA_MEM_2_SIZE) > (DDR3_BASE_ADDR_1 + DDR3_BASE_SIZE_1))
        {
            throw xdc.$$XDCException("MEMORY_MAP OVERFLOW ERROR ",
                               "\nRegion End: " + "0x" + java.lang.Long.toHexString(DDR3_BASE_ADDR_1 + DDR3_BASE_SIZE_1) +
                               "\nActual End: " + "0x" + java.lang.Long.toHexString(HDVPSS_DESC_ADDR + HDVPSS_DESC_SIZE));
        }
    }
*/
    if ((DDR3_BASE_SIZE_1 + DDR3_BASE_SIZE_0) > (TOTAL_MEM_SIZE))
    {
      throw xdc.$$XDCException("MEMORY_MAP EXCEEDS DDR SIZE ERROR ",
                               "\nRegion End: " + "0x" + java.lang.Long.toHexString(DDR3_BASE_SIZE_1 + DDR3_BASE_SIZE_0) +
                               "\nActual End: " + "0x" + java.lang.Long.toHexString(TOTAL_MEM_SIZE));
    }

    var memory = new Array();
    var index = 0;

    memory[index++] = ["IPU1_1_CODE_MEM", {
            comment : "IPU1_1_CODE_MEM",
            name    : "IPU1_1_CODE_MEM",
            base    : IPU1_1_CODE_ADDR,
            len     : IPU1_1_CODE_SIZE
        }];
    memory[index++] = ["IPU1_1_DATA_MEM", {
            comment : "IPU1_1_DATA_MEM",
            name    : "IPU1_1_DATA_MEM",
            base    : IPU1_1_DATA_ADDR,
            len     : IPU1_1_DATA_SIZE
        }];
    memory[index++] = ["IPU1_0_CODE_MEM", {
            comment : "IPU1_0_CODE_MEM",
            name    : "IPU1_0_CODE_MEM",
            base    : IPU1_0_CODE_ADDR,
            len     : IPU1_0_CODE_SIZE
        }];
    memory[index++] = ["IPU1_0_DATA_MEM", {
            comment : "IPU1_0_DATA_MEM",
            name    : "IPU1_0_DATA_MEM",
            base    : IPU1_0_DATA_ADDR,
            len     : IPU1_0_DATA_SIZE
        }];
    memory[index++] = ["DSP1_CODE_MEM", {
            comment : "DSP1_CODE_MEM",
            name    : "DSP1_CODE_MEM",
            base    : DSP1_CODE_ADDR,
            len     : DSP1_CODE_SIZE
        }];
    memory[index++] = ["DSP1_DATA_MEM", {
            comment : "DSP1_DATA_MEM",
            name    : "DSP1_DATA_MEM",
            base    : DSP1_DATA_ADDR,
            len     : DSP1_DATA_SIZE
        }];
    memory[index++] = ["DSP1_DATA_MEM_2", {
            comment : "DSP1_DATA_MEM_2",
            name    : "DSP1_DATA_MEM_2",
            base    : DSP1_DATA_ADDR_2,
            len     : DSP1_DATA_SIZE_2
        }];

    memory[index++] = ["DSP2_CODE_MEM", {
            comment : "DSP2_CODE_MEM",
            name    : "DSP2_CODE_MEM",
            base    : DSP2_CODE_ADDR,
            len     : DSP2_CODE_SIZE
        }];
    memory[index++] = ["DSP2_DATA_MEM", {
            comment : "DSP2_DATA_MEM",
            name    : "DSP2_DATA_MEM",
            base    : DSP2_DATA_ADDR,
            len     : DSP2_DATA_SIZE
        }];
    memory[index++] = ["DSP2_DATA_MEM_2", {
            comment : "DSP2_DATA_MEM_2",
            name    : "DSP2_DATA_MEM_2",
            base    : DSP2_DATA_ADDR_2,
            len     : DSP2_DATA_SIZE_2
        }];

    memory[index++] = ["NDK_MEM", {
            comment : "NDK_MEM",
            name    : "NDK_MEM",
            base    : NDK_DATA_ADDR,
            len     : NDK_DATA_SIZE
        }];
    memory[index++] = ["EVE1_VECS_MEM", {
            comment : "EVE1_VECS_MEM",
            name    : "EVE1_VECS_MEM",
            base    : EVE1_VECS_ADDR,
            len     : EVE1_VECS_SIZE
        }];
    memory[index++] = ["EVE1_CODE_MEM", {
            comment : "EVE1_CODE_MEM",
            name    : "EVE1_CODE_MEM",
            base    : EVE1_CODE_ADDR,
            len     : EVE1_CODE_SIZE
        }];
    memory[index++] = ["EVE1_DATA_MEM", {
            comment : "EVE1_DATA_MEM",
            name    : "EVE1_DATA_MEM",
            base    : EVE1_DATA_ADDR,
            len     : EVE1_DATA_SIZE
        }];
    memory[index++] = ["SR1_FRAME_BUFFER_MEM", {
            comment : "SR1_FRAME_BUFFER_MEM",
            name    : "SR1_FRAME_BUFFER_MEM",
            base    : SR1_FRAME_BUFFER_ADDR,
            len     : SR1_FRAME_BUFFER_SIZE
        }];
    memory[index++] = ["SR1_BUFF_ECC_ASIL_MEM", {
            comment : "SR1_BUFF_ECC_ASIL_MEM",
            name    : "SR1_BUFF_ECC_ASIL_MEM",
            base    : SR1_BUFF_ECC_ASIL_ADDR,
            len     : SR1_BUFF_ECC_ASIL_SIZE
    }];
    memory[index++] = ["SR1_BUFF_ECC_QM_MEM", {
            comment : "SR1_BUFF_ECC_QM_MEM",
            name    : "SR1_BUFF_ECC_QM_MEM",
            base    : SR1_BUFF_ECC_QM_ADDR,
            len     : SR1_BUFF_ECC_QM_SIZE
    }];
    memory[index++] = ["SR1_BUFF_NON_ECC_ASIL_MEM", {
            comment : "SR1_BUFF_NON_ECC_ASIL_MEM",
            name    : "SR1_BUFF_NON_ECC_ASIL_MEM",
            base    : SR1_BUFF_NON_ECC_ASIL_ADDR,
            len     : SR1_BUFF_NON_ECC_ASIL_SIZE
    }];
    memory[index++] = ["SR0", {
            comment : "SR0",
            name    : "SR0",
            base    : SR0_ADDR,
            len     : SR0_SIZE
        }];
    memory[index++] = ["HDVPSS_DESC_MEM", {
            comment : "HDVPSS_DESC_MEM",
            name    : "HDVPSS_DESC_MEM",
            base    : HDVPSS_DESC_ADDR,
            len     : HDVPSS_DESC_SIZE
        }];
    memory[index++] = ["REMOTE_LOG_MEM", {
            comment : "REMOTE_LOG_MEM",
            name    : "REMOTE_LOG_MEM",
            base    : REMOTE_LOG_ADDR,
            len     : REMOTE_LOG_SIZE
        }];
    memory[index++] = ["LINK_STATS_MEM", {
            comment : "LINK_STATS_MEM",
            name    : "LINK_STATS_MEM",
            base    : LINK_STATS_ADDR,
            len     : LINK_STATS_SIZE
        }];
    memory[index++] = ["SYSTEM_IPC_SHM_MEM", {
            comment : "SYSTEM_IPC_SHM_MEM",
            name    : "SYSTEM_IPC_SHM_MEM",
            base    : SYSTEM_IPC_SHM_ADDR,
            len     : SYSTEM_IPC_SHM_SIZE
        }];

    xdc.print("# !!! Core is [" + core + "] !!!" );

    if( core == "arp32_1" )
    {
            memory[index++] = ["OCMC_RAM1", {
                    comment: "OCMC_RAM1",
                    name: "OCMC_RAM1",
                    base: OCMC1_ADDR,
                    len:  OCMC1_SIZE
                }];
    }
    memory[index++] = ["DSP1_L2_SRAM", {
            comment: "DSP1_L2_SRAM",
            name: "DSP1_L2_SRAM",
            base: DSP1_L2_SRAM_ADDR,
            len:  DSP1_L2_SRAM_SIZE
        }];
    memory[index++] = ["DSP2_L2_SRAM", {
            comment: "DSP2_L2_SRAM",
            name: "DSP2_L2_SRAM",
            base: DSP2_L2_SRAM_ADDR,
            len:  DSP2_L2_SRAM_SIZE
        }];
    if(java.lang.System.getenv("OPENVX_INCLUDE")=="yes")
    {
        memory[index++] = ["OPENVX_SHM_MEM", {
                comment: "OPENVX_SHM_MEM",
                name: "OPENVX_SHM_MEM",
                base: OPENVX_SHM_ADDR,
               len:  OPENVX_SHM_SIZE
        }];
    }

    return (memory);
}

0 Rishabh Garg over 5 years ago in reply to YiTing

TI__Guru 55685 points

Hi,

Can you confirm if you have all the changes described in section "6.5 How To – Modify 512MB Bios Memory map to 1GB Bios Memory map" of PROCESSOR_SDK_VISION_03_04_00_00\vision_sdk\docs\FeatureSpecificUserGuides\VisionSDK_UserGuide_MemoryMap.pdf.

If this also doesn't help then you need to connect different CPUs using CCS (make sure there is no gel) and then load symbols to identify the CPU that is crashing.

Regards,

Rishabh

0 YiTing over 5 years ago in reply to Rishabh Garg

Expert 1200 points

Hil,

The section "6.5 How To – Modify 512MB Bios Memory map to 1GB Bios Memory map" is no help to me,

Can you descibe "using CCS (make sure there is no gel) and then load symbols to identify the CPU that is crashing."

In my understanding , Can't connect Resume without "gel"

Press boad button(Avoid entering qspi) -> open CCS8 connect Target -> remove all gel ->

load symbols

0 Rishabh Garg over 5 years ago in reply to YiTing

TI__Guru 55685 points

Hi,

After trying the boot you will get only SBL prints and there is no SDK print.

Then launch the target configuration from the CCS.

Remove gels from all cores by using remove option from Gel menu.

Then connect to all 5 CPUs, load symbols and see what is the state of each CPU.

Regards,

Rishabh

0 YiTing over 5 years ago in reply to Rishabh Garg

Expert 1200 points

Hi,

Your mean like this below step?

1. qspi write SBL do not qspi write appimage

2. Power off

3. Power on

4. TTL print SBL message

5.open ccs remove all gel

6. connect target 5cpus

7. load symbol(vision_sdk_ipu1_0_release.xem4、vision_sdk_ipu1_1_release.xem4、vision_sdk_c66xdsp_1_release.xe66) to cpus

0 Rishabh Garg over 5 years ago in reply to YiTing

TI__Guru 55685 points

Hi,

In step one you need to write both app image and SBL. Remaining steps are same.

Regards,

Rishabh

0 YiTing over 5 years ago in reply to YiTing

Expert 1200 points

Hi,

The step is ok?

I have some question about it ,

What is the use of load symbol ?

How to find the crashing in cpu?

The print "Jumping to IPU1 CPU1 App" in the file path "sbl_lib_tda3xx_platform.c"

0 Rishabh Garg over 5 years ago in reply to YiTing

TI__Guru 55685 points

Hi,

You need to remove gel from all CPUs before trying to connect.

Regards,

Rishabh

0 YiTing over 5 years ago in reply to Rishabh Garg

Expert 1200 points

Hi ,

The is step ok!

but i donnot knowe the next How to find the crashing in cpu?

0 YiTing over 5 years ago in reply to YiTing

Expert 1200 points

The final print "Jumping to IPU1 CPU1 App"

Path"C:\PROCESSOR_SDK_VISION_03_04_00_00\ti_components\drivers\pdk_01_10_00_08\packages\ti\boot\sbl_auto\old sbl code\sbl_lib\src\tda3xx\ sbl_lib_tda3xx_platform.c"

So i need to trce SBL use ccs

0 Rishabh Garg over 5 years ago in reply to YiTing

TI__Guru 55685 points

Hi,

Sorry for the delayed response.

I will try this next week and get back to you.

Regards,

Rishabh

0 YiTing over 5 years ago in reply to Rishabh Garg

Expert 1200 points

HI,

Thank you for your reply, look forward to your answer.

0 Rishabh Garg over 5 years ago in reply to YiTing

TI__Guru 55685 points

Hi,

Are you using EVM or some custom board?

Regards,

Rishabh

0 YiTing over 5 years ago in reply to Rishabh Garg

Expert 1200 points

hi,

I use custom board

0 Rishabh Garg over 5 years ago in reply to YiTing

TI__Guru 55685 points

Hi,

Can you confirm if there is 1 GB DDR on your board.

EVM has only 512 MB DDR and 512 MB configuration works fine there.

TDA3 RVP board has 1 GB DDR and 1 GB configuration is working fine on this board.

Regards,

Rishabh

0 YiTing over 5 years ago in reply to Rishabh Garg

Expert 1200 points

I have two 512MB DDR

If set DDR_MEM=DDR_MEM_512M in C:\PROCESSOR_SDK_VISION_03_04_00_00\vision_sdk\apps\configs\tda3xx_evm_bios_all\cfg.mk

work well .

If set DDR_MEM=DDR_MEM_1024M , does not work in

Jumping to IPU1 CPU1 App

Jumping to IPU1 CPU0 App

My chge code below :

Change DDR_MEM variable in
C:\PROCESSOR_SDK_VISION_03_04_00_00\vision_sdk\apps\configs\tda3xx_evm_bios_all\cfg.mk

EMIF SIZE in 512MB to 1024MB
C:\PROCESSOR_SDK_VISION_03_04_00_00\ti_components\drivers\pdk_01_10_00_08\packages\ti\boot\sbl_auto\sbl_lib\src\tda3xx\sbl_lib_config_tda3xx.h

DDR EMIF set of EMIFtool
C:\PROCESSOR_SDK_VISION_03_04_00_00\ti_components\drivers\pdk_01_10_00_08\packages\ti\boot\sbl_auto\sbl_utils\src\tda3xx

0 Rishabh Garg over 5 years ago in reply to YiTing

TI__Guru 55685 points

Hi,

Can you build for tda3xx_rvp_bios_all and then try. In this particular configuration we are setting 1 GB DDR.

You don't need to make any changes when you build for RVP. Also make sure that you rebuild SBL.

Regards,

Rishabh

0 YiTing over 5 years ago in reply to Rishabh Garg

Expert 1200 points

Hi,

I change the Path : "C:\PROCESSOR_SDK_VISION_03_04_00_00\vision_sdk\build\Rules.make" ,

" MAKECONFIG?=tda3xx_evm_bios_all " to "MAKECONFIG?=tda3xx_rvp_bios_all"

rebuild the sbl and app use command :

gmake clean

gmake sbl

gmake -s

gmake appimage

burn the qspi use ccs

stil crash in Jumping to IPU1 CPU0 App

0 YiTing over 5 years ago in reply to Rishabh Garg

Expert 1200 points

Our previous bios was using evm,
Can I use DDR 1024mb ddr without replace bios?

0 Rishabh Garg over 5 years ago in reply to YiTing

TI__Guru 55685 points

Hi,

RVP support 1 GB DDR and hence I had asked you to try with same.

It is possible that DDR is not stable on custom board.

Is 512 MB boot working fine?

I did not understand "Can I use DDR 1024mb ddr without replace bios?".

Regards,

Rishabh

0 YiTing over 5 years ago in reply to Rishabh Garg

Expert 1200 points

HI,

The 512MB is working fine on tda3xx_evm_bios_all.

We custom boad used tda3xx_evm_bios_all , Can we use DDR1024MB with tda3xx_evm_bios_all ?

0 Rishabh Garg over 5 years ago in reply to YiTing

TI__Guru 55685 points

Hi,

Yes you can use. But this is not something TI can validate as our EVM has only 512 MB.

We have RVP board on which we have validated 1 GB as the same board has 1 GB DDR.

Can you check if the memory from 0xA0000000 to 0xC0000000 is stable on your custom board?

You can use CCS and the memory browser.

Regards,

Rishabh

0 YiTing over 5 years ago in reply to Rishabh Garg

Expert 1200 points

HI,

Thanks your reply very help for me,

I have some question about,

If I want to use bios "rvp_bios_all " the step is correct??

Step:

I change the Path : "C:\PROCESSOR_SDK_VISION_03_04_00_00\vision_sdk\build\Rules.make" ,

" MAKECONFIG?=tda3xx_evm_bios_all " to "MAKECONFIG?=tda3xx_rvp_bios_all"

rebuild the sbl and appimage use command :

>gmake clean

>gmake sbl

>gmake -s

>gmake appimage

burn the qspi use ccs load IPU1_0 : "PPROCESSOR_SDK_VISION_03_04_00_00\vision_sdk\build\rtos\scripts\tda3xxrvp\qspiFlashWriter_m4_release.xem4"

burn the appimage use ccs load "IPU1_0 : PROCESSOR_SDK_VISION_03_04_00_00\vision_sdk\build\rtos\scripts\tda3xx-rvp\qspiFlashWriter_m4_release.xem4"

0 Rishabh Garg over 5 years ago in reply to YiTing

TI__Guru 55685 points

Hi,

I have updated the steps mentioned above:

Change the Path in "C:\PROCESSOR_SDK_VISION_03_04_00_00\vision_sdk\build\Rules.make" ,

" MAKECONFIG?=tda3xx_evm_bios_all " to "MAKECONFIG?=tda3xx_rvp_bios_all"

>rm -rf binaries

>gmake clean

>gmake -s depend

>gmake sbl

>gmake -s

>gmake appimage

burn the qspi use ccs load IPU1_0 : "PPROCESSOR_SDK_VISION_03_04_00_00\vision_sdk\build\rtos\scripts\tda3xxrvp\qspiFlashWriter_m4_release.xem4"

burn the appimage use ccs load "IPU1_0 : PROCESSOR_SDK_VISION_03_04_00_00\vision_sdk\build\rtos\scripts\tda3xx-rvp\qspiFlashWriter_m4_release.xem4"

Regards,

Rishabh

0 YiTing over 5 years ago in reply to Rishabh Garg

Expert 1200 points

HI,

I trace the datasheet path "IPU1_0 : PROCESSOR_SDK_VISION_03_04_00_00\vision_sdk\build\rtos\scripts\tda3xx-rvp\qspiFlashWriter_m4_release.xem4" use sdcard burn the appimage .

Q1 : How can I burn the appimge to qspi with CCS Instead of sdcard?

Q2 : How can I use DDR1024MB with tda3xx_evm_bios_all ??

I hope you provide detailed steps　, Thank you so much

0 Rishabh Garg over 5 years ago in reply to YiTing

TI__Guru 55685 points

Hi,

You need to use QSPI flash writer with CCS to flash the SBL and AppImage to QSPI flash.

There is no way to flash from SD card.

Also I have already explained to use tda3xx_rvp_bios_all for 1 GB configuration.

Regards,

Rishabh

0 Luke Lin over 5 years ago in reply to YiTing

TI__Expert 3250 points

As Rishabh mentioned, please check if your DDR is stable or not. PDK includes a DDR stress test program, I suggest running it firstly. Steps below

1. Apply your change (for 1GB) to “C:\ti\ccsv8\ccs_base\emulation\gel\TDA3x\TDA3xx_ddr_config.gel”

2. Build and run DDR stress test application

steps below
a. cd C:\PROCESSOR_SDK_VISION_03_07_00_00\ti_components\drivers\pdk_01_10_03_07\packages\ti\build

b. modify Rules.make

ifeq ($(OS),Windows_NT)
export utils_PATH ?= c:/ti/ccsv8/utils/cygwin
endif

c. set PATH=C:\PROCESSOR_SDK_VISION_03_07_00_00\ti_components\os_tools\windows\xdctools_3_32_01_22_core;%PATH%

d. gmake CORE=ipu1_0 BOARD=tda3xx-evm BUILD_PROFILE=debug examples

e. binary will be generated under C:\PROCESSOR_SDK_VISION_03_07_00_00\ti_components\drivers\pdk_01_10_03_07\packages\ti\binary\csl_ddr_test_app\bin\tda3xx-evm\csl_ddr_test_app_ipu1_0_debug.xem4

f. Use CCS to load and run csl_ddr_test_app_ipu1_0_debug.xem4

g. To test full 1GB memory size, you may need to modify the source code at the following location, rebuild and retest C:\PROCESSOR_SDK_VISION_03_07_00_00\ti_components\drivers\pdk_01_10_03_07\packages\ti\csl\example\ddr\ddr_test_app

Regarding to your question

Q1 : How can I burn the appimge to qspi with CCS Instead of sdcard?

Please check TDA3x user guide (under \vision_sdk\docs\UserGuides) chap 3.5 Load using QSPI

Q2 : How can I use DDR1024MB with tda3xx_evm_bios_all ??

DDR config is done in SBL. App has nothing to do with this. The memory map for the App tda3xx_evm_bios_all uses only 512MB, it should work on 1GB. However, the App will use only 512MB, it is required to modify memory map to fully utilize 1GB.

0 YiTing over 5 years ago in reply to Luke Lin

Expert 1200 points

Thanks for your help , it is very help for me,

I chang evm to RVP and work well,

I will try to check memory stable ,

Thanks ａ lot !!

0 Rishabh Garg over 5 years ago in reply to YiTing

TI__Guru 55685 points

Hi,

Thanks for the confirmation.

In case you have further questions please start a new thread, I am closing this one.

Regards,

Rishabh

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RTOS/TDA3XEVM: How to change ddr from 512MB to 1024MB?