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CCS/AM4379: Undefined instruction in pow()

Part Number: AM4379
Other Parts Discussed in Thread: SYSBIOS

Tool/software: Code Composer Studio

Dear support,

I have strange behavior with math.h GNU pow() function.

It chresh with "ti.sysbios.family.arm.exc.Exception: line 209: E_undefinedInstruction"
I'm not assembler expert so please help me understand what is going on....


...
dTmp = 1.0;
dTmp += (double)indexOrder;
gainBn[x]  = pow(dTmp, (double)-1.5);
...

make asm code:
1138          	dTmp = 1.0;
8003e150:   E3A02000            mov        r2, #0
8003e154:   E3A03000            mov        r3, #0
8003e158:   E3433FF0            movt       r3, #0x3ff0
8003e15c:   E14B21FC            strd       r2, r3, [r11, #-0x1c]
1139          	dTmp += (double)indexOrder;
8003e160:   E51B3010            ldr        r3, [r11, #-0x10]
8003e164:   EE073A90            vmov       s15, r3
8003e168:   EEF80BE7            vcvt.f64.s32 d16, s15
8003e16c:   ED5B1B07            vldr       d17, [r11, #-0x1c]
8003e170:   EE710BA0            vadd.f64   d16, d17, d16
8003e174:   ED4B0B07            vstr       d16, [r11, #-0x1c]
1140          	gainBn[x]  = pow(dTmp, (double)-1.5);
8003e178:   ED1B0B07            vldr       d0, [r11, #-0x1c]
8003e17c:   EEBF1B08            vmov.f64   d1, #-1.500000e+00
8003e180:   EB02B21A            bl         pow



AND IN POW() FUNCTION:

          pow():
800ea9f0:   E92D4030            push       {r4, r5, lr}
800ea9f4:   ED2D8B08            vpush      {d8, d9, d10, d11}
800ea9f8:   E24DD02C            sub        sp, sp, #0x2c
800ea9fc:   EEB0AB40            vmov.f64   d10, d0
800eaa00:   EEB09B41            vmov.f64   d9, d1
800eaa04:   EB0005E7            bl         __ieee754_pow
800eaa08:   E59F43B8            ldr        r4, [pc, #0x3b8]
800eaa0c:   E1D430D0            ldrsb      r3, [r4]
....

fail on :
800ea9fc:   EEB0AB40            vmov.f64   d10, d0

So why vmov.f64 is undefined instruction?

Also I wonder how I can see dX registers for debuging... ( ccsv7).. In "Registers" they are not visible...

Best Regards,

Mare

  • Hi,


    I try to use powf() and (float) variables and it is survive....

    Is something going on with double size operations?
  • COuld you indicate the version of SYSBIOS you are using and the version of the GNU GCC. I also recommend that you confirm that you are using the following float flags with GCC and make sure that you understand the impact of the newlib nano libc used in SYSBIOS 6.51 and later.

    processors.wiki.ti.com/.../BIOS_with_GCC_(CortexA)

    Regards,
    Rahul
  • -bios_6_46_04_53

    -GNU v4.9.3 (Linaro)

     I also recommend that you confirm that you are using the following float flags with GCC

    Which floating flags?

    My current compiler cmd:

    -mcpu=cortex-a9 -mtune=cortex-a9 -march=armv7-a -marm -mfloat-abi=hard -mfpu=neon -Dam4379 -DSOC_AM437x -Dcore0 -DPTP_TESTING -DBUILD_PRP -DRED_STATS_DBG -DIPC_CUSTOM_SPI ... -O0 -ffunction-sections -fdata-sections -g -gdwarf-2 -gstrict-dwarf -Wall -mno-unaligned-access

  • Hi,

    I getting exception depends on some minor changes in C code and build...

    Now I'm getting exception on "vadd.f32   s15, s14, s15" inside main (before TI-RTOS is started)

    1142          	dTmp += (float)indexOrder;
    800401a0:   E51B3010            ldr        r3, [r11, #-0x10]
    800401a4:   EE073A90            vmov       s15, r3
    800401a8:   EEF87AE7            vcvt.f32.s32 s15, s15
    800401ac:   ED1B7A06            vldr       s14, [r11, #-0x18]
    800401b0:   EE777A27            vadd.f32   s15, s14, s15
    800401b4:   ED4B7A06            vstr       s15, [r11, #-0x18]

    Am I doing something obvious wrong??
    What I can also check? I attach gcc settings in the previous post.
    I'm too "short" in knowledge of FPU/NEON ....

    Please point me somewhere.

    Best Regards,
    Mare  

  • Sorry for the delay in responding to this issue. Let me loop folks from our compiler team to comment on this issue. 

    Regards,

    Rahul