Tool/software: Linux
Hi Champs:
We have a customer to use marvell 88e6176 RGMII mode on the uboot.
However, we measure the Signal during the uBoot stage, we cannot see the TX0/1/2/3 signal, nor the TX Enable.
A. They are using the SDK2 version.
B. Code on the board.c is as below:
static struct module_pin_mux rgmii2_pin_mux_moxa_tau[] = {
{OFFSET(gpmc_a0), MODE(2)}, /* RGMII2_TCTL */
{OFFSET(gpmc_a1), MODE(2) | RXACTIVE}, /* RGMII2_RCTL */
{OFFSET(gpmc_a2), MODE(2)}, /* RGMII2_TD3 */
{OFFSET(gpmc_a3), MODE(2)}, /* RGMII2_TD2 */
{OFFSET(gpmc_a4), MODE(2)}, /* RGMII2_TD1 */
{OFFSET(gpmc_a5), MODE(2)}, /* RGMII2_TD0 */
{OFFSET(gpmc_a6), MODE(2)}, /* RGMII2_TCLK */
{OFFSET(gpmc_a7), MODE(2) | RXACTIVE}, /* RGMII2_RCLK */
{OFFSET(gpmc_a8), MODE(2) | RXACTIVE}, /* RGMII2_RD3 */
{OFFSET(gpmc_a9), MODE(2) | RXACTIVE}, /* RGMII2_RD2 */
{OFFSET(gpmc_a10), MODE(2) | RXACTIVE}, /* RGMII2_RD1 */
{OFFSET(gpmc_a11), MODE(2) | RXACTIVE}, /* RGMII2_RD0 */
{-1},
};
C. We have reviewed the schematic / PinMux, it should be correct.
May you guide us what's the possible root cause to mulfunction?
Attached is the uboot log, and the c file to review.
THanks.
BR Rio
U-Boot 2016.01-gffbd375-dirty (Jun 03 2019 - 15:10:21 +0800)
Watchdog enabled
I2C: ready
DRAM: 1 GiB
MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1, OMAP SD/MMC: 2
SF: Detected MX25L6405D with page size 256 Bytes, erase size 64 KiB, total 8 MiB
*** Warning - bad CRC, using default environment
SF: Detected MX25L6405D with page size 256 Bytes, erase size 64 KiB, total 8 MiB
!bad CRC
Net: Could not get PHY for cpsw0: addr 4
cpsw0, cpsw1
Saving Environment to SPI Flash...
SF: Detected MX25L6405D with page size 256 Bytes, erase size 64 KiB, total 8 MiB
Erasing SPI flash...Writing to SPI flash...done
Valid environment: 2
Saving Environment to SPI Flash...
Erasing SPI flash...Writing to SPI flash...done
Valid environment: 1
Press <DEL> To Enter BIOS configuration Setting: 1
----------------------------------------------------------------------------
Model: UC-8100A-ME-T-LX
Boot Loader Version: 1.0.0S16 CPU TYPE: 1000MHz
Build date: Jun 3 2019 - 15:10:26 Serial Number: IMOXA1234567
LAN1 MAC: 00:90:e8:00:00:41 LAN2 MAC: 00:90:e8:00:00:42
----------------------------------------------------------------------------
(0) Set/Clear Flag (1) Download/Upload
(2) Set SN/MAC (3) Set Burn in Time
(4) Module/ID Setting (5) TFTP Settings
(6) Console/UART Test (7) Ethernet Test
(8) IO Test (9) Memory/Storage Test
(a) TPM2 Setting (b) RTC Test
(c) USB Host Test (d) SD Test
(e) LED Test (f) WDT Test
(g) Set/Clear backup env (h) QA Test
(i) Run Kernel (q) UBoot Command Line
---------------------------------------------------------------------------
Command>>****************************************************************
----------------------------------------------------------------------------
Model: UC-8100A-ME-T-LX
Boot Loader Version: 1.0.0S16 CPU TYPE: 1000MHz
Build date: Jun 3 2019 - 15:10:26 Serial Number: IMOXA1234567
LAN1 MAC: 00:90:e8:00:00:41 LAN2 MAC: 00:90:e8:00:00:42
----------------------------------------------------------------------------
(0) Set/Clear Flag (1) Download/Upload
(2) Set SN/MAC (3) Set Burn in Time
(4) Module/ID Setting (5) TFTP Settings
(6) Console/UART Test (7) Ethernet Test
(8) IO Test (9) Memory/Storage Test
(a) TPM2 Setting (b) RTC Test
(c) USB Host Test (d) SD Test
(e) LED Test (f) WDT Test
(g) Set/Clear backup env (h) QA Test
(i) Run Kernel (q) UBoot Command Line
---------------------------------------------------------------------------
Command>>q
=> print
baudrate=115200
biosver=1.0.0S16
board_name=UC8100A
board_rev=1.2B
bootargs=mac=00:90:E8:40:4C:FD sd=1 ver=1 console=ttyO0,115200n8 root=/dev/mmcblk0p2 rootfstype=ext4 rootwait
bootcmd=run findfdt; run distro_bootcmd
bootdelay=1
cell_flags=0
en_tpm2=1
eth1addr=00:90:e8:00:00:42
ethact=cpsw0
ethaddr=00:90:e8:00:00:41
fastboot=0
fdt_high=0x9fffffff
ifnames=0
ipaddr=10.144.5.44
mm_flags=0
mmcdev=1
modelname=UC-8100A-ME-T-LX
os_boot_priority=0
overlay_flag=v1
realtime=0
robust=0
sd_protected=0
serialnumber=IMOXA1234567
serverip=10.144.5.36
stderr=serial
stdin=serial
stdout=serial
tpm2=0
Environment size: 651/131067 bytes
=> setenv ethact cpsw1
=> ping 192.168.127.100
Using cpsw1 device
Abort
ping failed; host 192.168.127.100 is not alive
=> ping 192.168.127.100
Using cpsw1 device
Abort
ping failed; host 192.168.127.100 is not alive
=> ping 192.168.127.100
Using cpsw1 device
Abort
ping failed; host 192.168.127.100 is not alive
=> ping 192.168.127.100
Using cpsw1 device
Abort
ping failed; host 192.168.127.100 is not alive
=> ping 192.168.127.100
Using cpsw1 device
Abort
ping failed; host 192.168.127.100 is not alive
=> mii info
PHY 0x10: OUI = 0x3FC005, Model = 0x36, Rev = 0x01, 1000baseX, HDX
PHY 0x11: OUI = 0x3FC005, Model = 0x36, Rev = 0x01, 1000baseX, HDX
PHY 0x12: OUI = 0x3FC005, Model = 0x36, Rev = 0x01, 1000baseX, HDX
PHY 0x13: OUI = 0x3FC005, Model = 0x36, Rev = 0x01, 1000baseX, HDX
PHY 0x14: OUI = 0x3FC005, Model = 0x36, Rev = 0x01, 1000baseX, HDX
PHY 0x15: OUI = 0x3FC005, Model = 0x36, Rev = 0x01, 1000baseX, HDX
PHY 0x16: OUI = 0x3FC005, Model = 0x36, Rev = 0x01, 1000baseX, HDX
PHY 0x1B: OUI = 0x0000, Model = 0x00, Rev = 0x00, 10baseT, HDX
PHY 0x1D: OUI = 0x0000, Model = 0x00, Rev = 0x00, 10baseT, HDX
=> mii read 0x1D 0x0
/*
* board.c
*
* Board functions for TI AM335X based boards
*
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <errno.h>
#include <spl.h>
#include <asm/arch/cpu.h>
#include <asm/arch/hardware.h>
#include <asm/arch/omap.h>
#include <asm/arch/ddr_defs.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mem.h>
#include <asm/io.h>
#include <asm/emif.h>
#include <asm/gpio.h>
#include <i2c.h>
#include <miiphy.h>
#include <cpsw.h>
#include <power/tps65217.h>
#include <power/tps65910.h>
#include <environment.h>
#include <watchdog.h>
#include <environment.h>
#include <model.h>
#include "board.h"
#include "types.h"
#include <wdt_ds1374.h>
#include <common.h>
#include "../../../common/moxa_bios/moxa_lib.h"
DECLARE_GLOBAL_DATA_PTR;
#define MAX_HW_INFO_SIZE 512
/* GPIO that controls power to DDR on EVM-SK */
#define GPIO_DDR_VTT_EN 7
#if defined(CONFIG_SPL_BUILD) || \
(defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_DM_ETH))
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
#endif
/*
* Read header information from EEPROM into global structure.
*/
static int read_eeprom(struct am335x_baseboard_id *header)
{
memset ((header), 0xff, sizeof (header));
header->magic = 0xEE3355AA;
memcpy ((header->name), "UC8100A", 7);
memcpy ((header->version), "1.2B", 4);
memcpy ((header->serial), "45124P196288", 12);
memcpy ((header->config), "SKU#00FFFFFFFFFFFFFFFFFFFFFFFFFF", 32);
return 0;
}
static int chk_hw_info(uchar *buf)
{
if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
puts("Could not probe the EEPROM; something fundamentally "
"wrong on the I2C bus.\n");
return -ENODEV;
}
/* read the eeprom using i2c */
if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)buf, MAX_HW_INFO_SIZE)) {
puts("Could not read the EEPROM; something fundamentally"
" wrong on the I2C bus.\n");
return -EIO;
}
return 0;
}
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
/*
static const struct ddr_data micron_MT41K128M16HA125_ddr3_data = {
.datardsratio0 = MT41K128M16HA125_RD_DQS,
.datawdsratio0 = MT41K128M16HA125_WR_DQS,
.datafwsratio0 = MT41K128M16HA125_PHY_FIFO_WE,
.datawrsratio0 = MT41K128M16HA125_PHY_WR_DATA,
};
static const struct cmd_control micron_MT41K128M16HA125_ddr3_cmd_ctrl_data = {
.cmd0csratio = MT41K128M16HA125_RATIO,
.cmd0iclkout = MT41K128M16HA125_INVERT_CLKOUT,
.cmd1csratio = MT41K128M16HA125_RATIO,
.cmd1iclkout = MT41K128M16HA125_INVERT_CLKOUT,
.cmd2csratio = MT41K128M16HA125_RATIO,
.cmd2iclkout = MT41K128M16HA125_INVERT_CLKOUT,
};
static struct emif_regs micron_MT41K128M16HA125_ddr3_emif_reg_data = {
.sdram_config = MT41K128M16HA125_EMIF_SDCFG,
.ref_ctrl = MT41K128M16HA125_EMIF_SDREF,
.sdram_tim1 = MT41K128M16HA125_EMIF_TIM1,
.sdram_tim2 = MT41K128M16HA125_EMIF_TIM2,
.sdram_tim3 = MT41K128M16HA125_EMIF_TIM3,
.zq_config = MT41K128M16HA125_ZQ_CFG,
.emif_ddr_phy_ctlr_1 = MT41K128M16HA125_EMIF_READ_LATENCY,
};
static const struct ddr_data UC2112_MT41K256M16HA125E_ddr3_data = {
.datardsratio0 = UC2112_MT41K256M16HA125E_RD_DQS,
.datawdsratio0 = UC2112_MT41K256M16HA125E_WR_DQS,
.datafwsratio0 = UC2112_MT41K256M16HA125E_PHY_FIFO_WE,
.datawrsratio0 = UC2112_MT41K256M16HA125E_PHY_WR_DATA,
};
static const struct cmd_control UC2112_MT41K256M16HA125E_ddr3_cmd_ctrl_data = {
.cmd0csratio = UC2112_MT41K256M16HA125E_RATIO,
.cmd0iclkout = UC2112_MT41K256M16HA125E_INVERT_CLKOUT,
.cmd1csratio = UC2112_MT41K256M16HA125E_RATIO,
.cmd1iclkout = UC2112_MT41K256M16HA125E_INVERT_CLKOUT,
.cmd2csratio = UC2112_MT41K256M16HA125E_RATIO,
.cmd2iclkout = UC2112_MT41K256M16HA125E_INVERT_CLKOUT,
};
static struct emif_regs UC2112_MT41K256M16HA125E_ddr3_emif_reg_data = {
.sdram_config = UC2112_MT41K256M16HA125E_EMIF_SDCFG,
.ref_ctrl = UC2112_MT41K256M16HA125E_EMIF_SDREF,
.sdram_tim1 = UC2112_MT41K256M16HA125E_EMIF_TIM1,
.sdram_tim2 = UC2112_MT41K256M16HA125E_EMIF_TIM2,
.sdram_tim3 = UC2112_MT41K256M16HA125E_EMIF_TIM3,
.zq_config = UC2112_MT41K256M16HA125E_ZQ_CFG,
.emif_ddr_phy_ctlr_1 = UC2112_MT41K256M16HA125E_EMIF_READ_LATENCY,
};
static const struct ddr_data UC8100A_MT41K512M16HA125E_ddr3_data = {
.datardsratio0 = UC8100A_MT41K512M16HA125E_RD_DQS,
.datawdsratio0 = UC8100A_MT41K512M16HA125E_WR_DQS ,
.datafwsratio0 = UC8100A_MT41K512M16HA125E_PHY_FIFO_WE,
.datawrsratio0 = UC8100A_MT41K512M16HA125E_PHY_WR_DATA,
};
static const struct cmd_control UC8100A_MT41K512M16HA125E_ddr3_cmd_ctrl_data = {
.cmd0csratio = UC8100A_MT41K512M16HA125E_RATIO,
.cmd0iclkout = UC8100A_MT41K512M16HA125E_INVERT_CLKOUT,
.cmd1csratio = UC8100A_MT41K512M16HA125E_RATIO,
.cmd1iclkout = UC8100A_MT41K512M16HA125E_INVERT_CLKOUT,
.cmd2csratio = UC8100A_MT41K512M16HA125E_RATIO,
.cmd2iclkout = UC8100A_MT41K512M16HA125E_INVERT_CLKOUT,
};
static struct emif_regs UC8100A_MT41K512M16HA125E_ddr3_emif_reg_data = {
.sdram_config = UC8100A_MT41K512M16HA125E_EMIF_SDCFG,
.ref_ctrl = UC8100A_MT41K512M16HA125E_EMIF_SDREF,
.sdram_tim1 = UC8100A_MT41K512M16HA125E_EMIF_TIM1,
.sdram_tim2 = UC8100A_MT41K512M16HA125E_EMIF_TIM2,
.sdram_tim3 = UC8100A_MT41K512M16HA125E_EMIF_TIM3,
.zq_config = UC8100A_MT41K512M16HA125E_ZQ_CFG,
.emif_ddr_phy_ctlr_1 = UC8100A_MT41K512M16HA125E_EMIF_READ_LATENCY,
};
*/
//======================= ISSI ===========================
static const struct ddr_data UC8100A_IS43TR16512BL_ddr3_data = {
.datardsratio0 = UC8100A_IS43TR16512BL_RD_DQS,
.datawdsratio0 = UC8100A_IS43TR16512BL_WR_DQS ,
.datafwsratio0 = UC8100A_IS43TR16512BL_PHY_FIFO_WE,
.datawrsratio0 = UC8100A_IS43TR16512BL_PHY_WR_DATA,
};
static const struct cmd_control UC8100A_IS43TR16512BL_ddr3_cmd_ctrl_data = {
.cmd0csratio = UC8100A_IS43TR16512BL_RATIO,
.cmd0iclkout = UC8100A_IS43TR16512BL_INVERT_CLKOUT,
.cmd1csratio = UC8100A_IS43TR16512BL_RATIO,
.cmd1iclkout = UC8100A_IS43TR16512BL_INVERT_CLKOUT,
.cmd2csratio = UC8100A_IS43TR16512BL_RATIO,
.cmd2iclkout = UC8100A_IS43TR16512BL_INVERT_CLKOUT,
};
static struct emif_regs UC8100A_IS43TR16512BL_ddr3_emif_reg_data = {
.sdram_config = UC8100A_IS43TR16512BL_EMIF_SDCFG,
.ref_ctrl = UC8100A_IS43TR16512BL_EMIF_SDREF,
.sdram_tim1 = UC8100A_IS43TR16512BL_EMIF_TIM1,
.sdram_tim2 = UC8100A_IS43TR16512BL_EMIF_TIM2,
.sdram_tim3 = UC8100A_IS43TR16512BL_EMIF_TIM3,
.zq_config = UC8100A_IS43TR16512BL_ZQ_CFG,
.emif_ddr_phy_ctlr_1 = UC8100A_IS43TR16512BL_EMIF_READ_LATENCY,
};
//======================= MT41K256M16HA125E ===========================
/*
static const struct ddr_data MT41K256M16HA125E_ddr3_data = {
.datardsratio0 = MT41K256M16HA125E_RD_DQS,
.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
};
static const struct cmd_control MT41K256M16HA125E_ddr3_cmd_ctrl_data = {
.cmd0csratio = MT41K256M16HA125E_RATIO,
.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
.cmd1csratio = MT41K256M16HA125E_RATIO,
.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
.cmd2csratio = MT41K256M16HA125E_RATIO,
.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
};
static struct emif_regs MT41K256M16HA125E_ddr3_emif_reg_data = {
.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
.zq_config = MT41K256M16HA125E_ZQ_CFG,
.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
};
*/
static const struct ddr_data MT41K512M16HA_ddr3_data = {
.datardsratio0 = MT41K512M16HA_RD_DQS,
.datawdsratio0 = MT41K512M16HA_WR_DQS,
.datafwsratio0 = MT41K512M16HA_PHY_FIFO_WE,
.datawrsratio0 = MT41K512M16HA_PHY_WR_DATA,
};
static const struct cmd_control MT41K512M16HA_ddr3_cmd_ctrl_data = {
.cmd0csratio = MT41K512M16HA_RATIO,
.cmd0iclkout = MT41K512M16HA_INVERT_CLKOUT,
.cmd1csratio = MT41K512M16HA_RATIO,
.cmd1iclkout = MT41K512M16HA_INVERT_CLKOUT,
.cmd2csratio = MT41K512M16HA_RATIO,
.cmd2iclkout = MT41K512M16HA_INVERT_CLKOUT,
};
static struct emif_regs MT41K512M16HA_ddr3_emif_reg_data = {
.sdram_config = MT41K512M16HA_EMIF_SDCFG,
.ref_ctrl = MT41K512M16HA_EMIF_SDREF,
.sdram_tim1 = MT41K512M16HA_EMIF_TIM1,
.sdram_tim2 = MT41K512M16HA_EMIF_TIM2,
.sdram_tim3 = MT41K512M16HA_EMIF_TIM3,
.zq_config = MT41K512M16HA_ZQ_CFG,
.emif_ddr_phy_ctlr_1 = MT41K512M16HA_EMIF_READ_LATENCY,
};
static const struct ddr_data moxa_ddr3_data = {
.datardsratio0 = K4B4G1646D_RD_DQS,
.datawdsratio0 = K4B4G1646D_WR_DQS,
.datafwsratio0 = K4B4G1646D_PHY_FIFO_WE,
.datawrsratio0 = K4B4G1646D_PHY_WR_DATA,
};
static const struct cmd_control moxa_ddr3_cmd_ctrl_data = {
.cmd0csratio = K4B4G1646D_RATIO,
.cmd0iclkout = K4B4G1646D_INVERT_CLKOUT,
.cmd1csratio = K4B4G1646D_RATIO,
.cmd1iclkout = K4B4G1646D_INVERT_CLKOUT,
.cmd2csratio = K4B4G1646D_RATIO,
.cmd2iclkout = K4B4G1646D_INVERT_CLKOUT,
};
static struct emif_regs moxa_ddr3_emif_reg_data = {
.sdram_config = K4B4G1646D_EMIF_SDCFG,
.ref_ctrl = K4B4G1646D_EMIF_SDREF,
.sdram_tim1 = K4B4G1646D_EMIF_TIM1,
.sdram_tim2 = K4B4G1646D_EMIF_TIM2,
.sdram_tim3 = K4B4G1646D_EMIF_TIM3,
.zq_config = K4B4G1646D_ZQ_CFG,
.emif_ddr_phy_ctlr_1 = K4B4G1646D_EMIF_READ_LATENCY,
};
static const struct ddr_data MT41K256M16TW107_ddr3_data = {
.datardsratio0 = MT41K256M16TW107_RD_DQS,
.datawdsratio0 = MT41K256M16TW107_WR_DQS,
.datafwsratio0 = MT41K256M16TW107_PHY_FIFO_WE,
.datawrsratio0 = MT41K256M16TW107_PHY_WR_DATA,
};
static const struct cmd_control MT41K256M16TW107_ddr3_cmd_ctrl_data = {
.cmd0csratio = MT41K256M16TW107_RATIO,
.cmd0iclkout = MT41K256M16TW107_INVERT_CLKOUT,
.cmd1csratio = MT41K256M16TW107_RATIO,
.cmd1iclkout = MT41K256M16TW107_INVERT_CLKOUT,
.cmd2csratio = MT41K256M16TW107_RATIO,
.cmd2iclkout = MT41K256M16TW107_INVERT_CLKOUT,
};
static struct emif_regs MT41K256M16TW107_ddr3_emif_reg_data = {
.sdram_config = MT41K256M16TW107_EMIF_SDCFG,
.ref_ctrl = MT41K256M16TW107_EMIF_SDREF,
.sdram_tim1 = MT41K256M16TW107_EMIF_TIM1,
.sdram_tim2 = MT41K256M16TW107_EMIF_TIM2,
.sdram_tim3 = MT41K256M16TW107_EMIF_TIM3,
.zq_config = MT41K256M16TW107_ZQ_CFG,
.emif_ddr_phy_ctlr_1 = MT41K256M16TW107_EMIF_READ_LATENCY,
};
#ifdef CONFIG_SPL_OS_BOOT
int spl_start_uboot(void)
{
*(volatile unsigned int *)(0x4804c134) = 0xefffffff;
*(volatile unsigned int *)(0x481ae134) = 0xffedffff;
return !((*(volatile unsigned int *)(0x481ae138))&0x200000);
}
#endif
#define OSC (V_OSCK/1000000)
const struct dpll_params dpll_ddr = {
266, OSC-1, 1, -1, -1, -1, -1};
const struct dpll_params dpll_ddr_evm_sk = {
303, OSC-1, 1, -1, -1, -1, -1};
const struct dpll_params dpll_ddr_bone_black = {
400, OSC-1, 1, -1, -1, -1, -1};
const struct dpll_params dpll_ddr_uc8100a = {
400, OSC-1, 1, -1, -1, -1, -1};
void am33xx_spl_board_init(void)
{
struct am335x_baseboard_id header;
int mpu_vdd;
if (read_eeprom(&header) < 0)
puts("Could not get board ID.\n");
/* Get the frequency */
dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
if (board_is_bone(&header) || board_is_bone_lt(&header)) {
/* BeagleBone PMIC Code */
int usb_cur_lim;
/*
* Only perform PMIC configurations if board rev > A1
* on Beaglebone White
*/
if (board_is_bone(&header) && !strncmp(header.version,
"00A1", 4))
return;
if (i2c_probe(TPS65217_CHIP_PM))
return;
/*
* On Beaglebone White we need to ensure we have AC power
* before increasing the frequency.
*/
if (board_is_bone(&header)) {
uchar pmic_status_reg;
if (tps65217_reg_read(TPS65217_STATUS,
&pmic_status_reg))
return;
if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) {
puts("No AC power, disabling frequency switch\n");
return;
}
}
/*
* Override what we have detected since we know if we have
* a Beaglebone Black it supports 1GHz.
*/
if (board_is_bone_lt(&header))
dpll_mpu_opp100.m = MPUPLL_M_1000;
/*
* Increase USB current limit to 1300mA or 1800mA and set
* the MPU voltage controller as needed.
*/
if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
} else {
usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
}
if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
TPS65217_POWER_PATH,
usb_cur_lim,
TPS65217_USB_INPUT_CUR_LIMIT_MASK))
puts("tps65217_reg_write failure\n");
/* Set DCDC3 (CORE) voltage to 1.125V */
if (tps65217_voltage_update(TPS65217_DEFDCDC3,
TPS65217_DCDC_VOLT_SEL_1125MV)) {
puts("tps65217_voltage_update failure\n");
return;
}
/* Set CORE Frequencies to OPP100 */
do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
/* Set DCDC2 (MPU) voltage */
if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
puts("tps65217_voltage_update failure\n");
return;
}
/*
* Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
* Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
*/
if (board_is_bone(&header)) {
if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
TPS65217_DEFLS1,
TPS65217_LDO_VOLTAGE_OUT_3_3,
TPS65217_LDO_MASK))
puts("tps65217_reg_write failure\n");
} else {
if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
TPS65217_DEFLS1,
TPS65217_LDO_VOLTAGE_OUT_1_8,
TPS65217_LDO_MASK))
puts("tps65217_reg_write failure\n");
}
if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
TPS65217_DEFLS2,
TPS65217_LDO_VOLTAGE_OUT_3_3,
TPS65217_LDO_MASK))
puts("tps65217_reg_write failure\n");
} else {
int sil_rev;
/*
* The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all
* MPU frequencies we support we use a CORE voltage of
* 1.1375V. For MPU voltage we need to switch based on
* the frequency we are running at.
*/
if (i2c_probe(TPS65910_CTRL_I2C_ADDR))
return;
/*
* Depending on MPU clock and PG we will need a different
* VDD to drive at that speed.
*/
sil_rev = readl(&cdev->deviceid) >> 28;
mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev,
dpll_mpu_opp100.m);
/* Tell the TPS65910 to use i2c */
tps65910_set_i2c_control();
/* First update MPU voltage. */
if (tps65910_voltage_update(MPU, mpu_vdd))
return;
/* Second, update the CORE voltage. */
if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
return;
/* Set CORE Frequencies to OPP100 */
do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
}
/* Set MPU Frequency to what we detected now that voltages are set */
do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
}
const struct dpll_params *get_dpll_ddr_params(void)
{
struct am335x_baseboard_id header;
enable_i2c0_pin_mux();
i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
if (read_eeprom(&header) < 0)
puts("Could not get board ID.\n");
if (board_is_evm_sk(&header))
return &dpll_ddr_evm_sk;
else if (board_is_bone_lt(&header))
return &dpll_ddr_bone_black;
else if (board_is_evm_15_or_later(&header))
return &dpll_ddr_evm_sk;
else
return &dpll_ddr_uc8100a;
}
void set_uart_mux_conf(void)
{
#if CONFIG_CONS_INDEX == 1
enable_uart0_pin_mux();
#elif CONFIG_CONS_INDEX == 2
enable_uart1_pin_mux();
#elif CONFIG_CONS_INDEX == 3
enable_uart2_pin_mux();
#elif CONFIG_CONS_INDEX == 4
enable_uart3_pin_mux();
#elif CONFIG_CONS_INDEX == 5
enable_uart4_pin_mux();
#elif CONFIG_CONS_INDEX == 6
enable_uart5_pin_mux();
#endif
}
void set_mux_conf_regs(void)
{
__maybe_unused struct am335x_baseboard_id header;
if (read_eeprom(&header) < 0)
puts("Could not get board ID.\n");
enable_board_pin_mux(&header);
}
const struct ctrl_ioregs ioregs_evmsk = {
.cm0ioctl = MT41J128MJT125_IOCTRL_VALUE,
.cm1ioctl = MT41J128MJT125_IOCTRL_VALUE,
.cm2ioctl = MT41J128MJT125_IOCTRL_VALUE,
.dt0ioctl = MT41J128MJT125_IOCTRL_VALUE,
.dt1ioctl = MT41J128MJT125_IOCTRL_VALUE,
};
const struct ctrl_ioregs ioregs_bonelt = {
.cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
.cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
.cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
.dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
.dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
};
const struct ctrl_ioregs ioregs_evm15 = {
.cm0ioctl = MT41J512M8RH125_IOCTRL_VALUE,
.cm1ioctl = MT41J512M8RH125_IOCTRL_VALUE,
.cm2ioctl = MT41J512M8RH125_IOCTRL_VALUE,
.dt0ioctl = MT41J512M8RH125_IOCTRL_VALUE,
.dt1ioctl = MT41J512M8RH125_IOCTRL_VALUE,
};
const struct ctrl_ioregs ioregs_mxcore = {
.cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
.cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
.cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
.dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
.dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
};
const struct ctrl_ioregs ioregs_uc2100 = {
.cm0ioctl = UC2100_MT41K256M16HA125E_IOCTRL_VALUE,
.cm1ioctl = UC2100_MT41K256M16HA125E_IOCTRL_VALUE,
.cm2ioctl = UC2100_MT41K256M16HA125E_IOCTRL_VALUE,
.dt0ioctl = UC2100_MT41K256M16HA125E_IOCTRL_VALUE,
.dt1ioctl = UC2100_MT41K256M16HA125E_IOCTRL_VALUE,
};
const struct ctrl_ioregs ioregs = {
.cm0ioctl = K4B4G1646D_IOCTRL_VALUE,
.cm1ioctl = K4B4G1646D_IOCTRL_VALUE,
.cm2ioctl = K4B4G1646D_IOCTRL_VALUE,
.dt0ioctl = K4B4G1646D_IOCTRL_VALUE,
.dt1ioctl = K4B4G1646D_IOCTRL_VALUE,
};
void wdt_restart(int second)
{
unsigned long t;
u8 wdt_tmp = 0;
//printf ("Set WDT Timeout to %ds\n", second);
t = second * 4096;
wdt_tmp = i2c_reg_read(DS1374_WDT_ADDR, DS1374_CONTROL_ADDR);
wdt_tmp &= ~DS1374_WDT_ENABLE;
i2c_reg_write(DS1374_WDT_ADDR, DS1374_CONTROL_ADDR, wdt_tmp);
//printf("Set WD Counter: %06lX\n", t);
i2c_reg_write (DS1374_WDT_ADDR, DS1374_WDT_COUNTER_0_ADDR, (t & 0xFF));
//printf("Set WD_COUNTER_BYTE_0 to %02lX\n", (t & 0xFF));
i2c_reg_write (DS1374_WDT_ADDR, DS1374_WDT_COUNTER_1_ADDR, ((t >> 8) & 0xFF));
//printf ("Set WD_COUNTER_BYTE_1 to %02lX\n", ((t >> 8) & 0xFF));
i2c_reg_write (DS1374_WDT_ADDR, DS1374_WDT_COUNTER_2_ADDR, ((t >> 16) & 0xFF));
//printf ("Set WD_COUNTER_BYTE_2 to %02lX\n", ((t >> 16) & 0xFF));
i2c_reg_write(DS1374_WDT_ADDR, DS1374_CONTROL_ADDR, wdt_tmp | DS1374_WDT_WDALM | DS1374_WDT_ENABLE);
// printf ("Enable WDT\n");
return;
}
void sdram_init(void)
{
__maybe_unused struct am335x_baseboard_id header;
uint32_t HWVersion = 0;
if (read_eeprom(&header) < 0)
puts("Could not get board ID.\n");
gpio_request (PIO_LED_MP_0, "DB0_LED");
gpio_request (PIO_LED_MP_1, "DB1_LED");
gpio_request (PIO_LED_MP_2, "DB2_LED");
gpio_request (PIO_LED_MP_3, "DB3_LED");
gpio_direction_output (PIO_LED_MP_0, 0);
gpio_direction_output (PIO_LED_MP_1, 0);
gpio_direction_output (PIO_LED_MP_2, 0);
gpio_direction_output (PIO_LED_MP_3, 0);
gpio_request (PIO_MPE_PEN, "CELL_PWR");
gpio_request (PIO_MPE_W_DIS, "CELL_DIS");
gpio_request (PIO_MPE_RST, "CELL_RST");
gpio_direction_output (PIO_MPE_PEN, 0);
gpio_direction_output (PIO_MPE_W_DIS, 0);
gpio_direction_output (PIO_MPE_RST, 0);
PEEPROMFORMAT eeprom_ptr;
uchar hw_ptr [MAX_HW_INFO_SIZE] = {0};
chk_hw_info(hw_ptr);
eeprom_ptr = (struct _EEPROMFORMAT *) hw_ptr;
if((eeprom_ptr->szMagic[0] == 0x55) && (eeprom_ptr->szMagic[1] == 0xAA)){
HWVersion = (eeprom_ptr->nHwMajorVersion1 << 8) |
(eeprom_ptr->nHwMinorVersion1 ) |
(eeprom_ptr->nHwMajorVersion2 << 16);
} else {
printf("Board-Info settings not saved in EEPROM\n");
}
if (eeprom_ptr->nHwMajorVersion2 == 0x2) {
// printf("TPM reset\n");
gpio_request (PIO_TPM_RST, "TPM2_RST");
gpio_direction_output (PIO_TPM_RST, 0);
udelay(500 * 1000);
gpio_direction_output (PIO_TPM_RST, 1);
udelay(500 * 1000);
gpio_direction_output (PIO_TPM_RST, 0);
}
wdt_restart(15);
/*
;nHwMajorVersion1
0xFF - SAMSUNG DDR3 256x16 = 512MB (1151256212111 K4B4G1646D-BCK0)
0x00 - SAMSUNG DDR3 256x16 = 512MB (1151256212111 K4B4G1646D-BCK0)
0x01 - Micron DDR3L 256x16 = 512MB (1151256212112 MT41K256M16TW)
0x02 - Micron DDR3L 128x16 = 256MB (1151128212113 MT41K128M16JT)
0x04 - Micron DDR3L 512x16 = 1GB (TBD)
0x05 - ISSI DDR3 512x16 = 1GB IS43TR16512BL)
;nHwMinorVersion1
0xFF - PCB version V1.0 (1199081000020 PCB UC-8100-ME V1.0 6L 135x128x1.2)
0x00 - PCB version V1.0 (1199081000020 PCB UC-8100-ME V1.0 6L 135x128x1.2)
*/
switch ((HWVersion >> 8) & 0x00ff ){ //only check DRAM setting
case 0xFF:
case 0x00: //assume SAMSUNG DDR3 512MB for no EEPROM acknowledge.
puts("Board: Unknown... DDR: IS43TR16512BL...");
config_ddr(400, &ioregs_uc2100,
&UC8100A_IS43TR16512BL_ddr3_data,
&UC8100A_IS43TR16512BL_ddr3_cmd_ctrl_data,
&UC8100A_IS43TR16512BL_ddr3_emif_reg_data, 0);
break;
case 0x01: //assume MICRON DDR3 512MB for no EEPROM acknowledge.
//for Micron MT41K256M16TW107
puts("Board: UC8100A-ME-T... DDR: MT41K256M16TW107...");
config_ddr(400, &ioregs_uc2100,
&MT41K256M16TW107_ddr3_data,
&MT41K256M16TW107_ddr3_cmd_ctrl_data,
&MT41K256M16TW107_ddr3_emif_reg_data, 0);
break;
case 0x04: //assume MICRON DDR3 1GB for no EEPROM acknowledge.
//for Micron MT41K512M16HA
puts("Board: UC8100A-ME-T... DDR: MT41K512M16HA...");
config_ddr(400, &ioregs_uc2100,
&MT41K512M16HA_ddr3_data,
&MT41K512M16HA_ddr3_cmd_ctrl_data,
&MT41K512M16HA_ddr3_emif_reg_data, 0);
break;
case 0x05: //assume ISSI DDR3 1GB for no EEPROM acknowledge.
//for Micron IS43TR16512BL...
puts("Board: UC8100A-ME-T... DDR: IS43TR16512BL...");
config_ddr(400, &ioregs_uc2100,
&UC8100A_IS43TR16512BL_ddr3_data,
&UC8100A_IS43TR16512BL_ddr3_cmd_ctrl_data,
&UC8100A_IS43TR16512BL_ddr3_emif_reg_data, 0);
break;
default:
puts("Board: Unknown... DDR: IS43TR16512BL...");
//for Samsung K4B4G1646D
config_ddr(400, &ioregs_uc2100,
&UC8100A_IS43TR16512BL_ddr3_data,
&UC8100A_IS43TR16512BL_ddr3_cmd_ctrl_data,
&UC8100A_IS43TR16512BL_ddr3_emif_reg_data, 0);
break;
}
puts("OK\n");
am33xx_spl_board_init();
}
#endif
/*
* Basic board specific setup. Pinmux has been handled already.
*/
int board_init(void)
{
#if defined(CONFIG_HW_WATCHDOG)
hw_watchdog_init();
#endif
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
#if defined(CONFIG_NOR) || defined(CONFIG_NAND)
gpmc_init();
#endif
return 0;
}
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
char safe_string[HDR_NAME_LEN + 1];
struct am335x_baseboard_id header;
if (read_eeprom(&header) < 0)
puts("Could not get board ID.\n");
/* Now set variables based on the header. */
strncpy(safe_string, (char *)header.name, sizeof(header.name));
safe_string[sizeof(header.name)] = 0;
setenv("board_name", safe_string);
/* BeagleBone Green eeprom, board_rev: 0x1a 0x00 0x00 0x00 */
if ( (header.version[0] == 0x1a) && (header.version[1] == 0x00) &&
(header.version[2] == 0x00) && (header.version[3] == 0x00) ) {
setenv("board_rev", "BBG1");
} else {
strncpy(safe_string, (char *)header.version, sizeof(header.version));
safe_string[sizeof(header.version)] = 0;
setenv("board_rev", safe_string);
}
#endif
return 0;
}
#endif
#ifndef CONFIG_DM_ETH
#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
static void cpsw_control(int enabled)
{
/* VTP can be added here */
return;
}
static struct cpsw_slave_data cpsw_slaves[] = {
{
.slave_reg_ofs = 0x208,
.sliver_reg_ofs = 0xd80,
.phy_addr = 0x4,
},
{
.slave_reg_ofs = 0x308,
.sliver_reg_ofs = 0xdc0,
.phy_addr = 0x16,
},
};
static struct cpsw_platform_data cpsw_data = {
.mdio_base = CPSW_MDIO_BASE,
.cpsw_base = CPSW_BASE,
.mdio_div = 0xff,
.channels = 8,
.cpdma_reg_ofs = 0x800,
.slaves = 1,
.slave_data = cpsw_slaves,
.ale_reg_ofs = 0xd00,
.ale_entries = 1024,
.host_port_reg_ofs = 0x108,
.hw_stats_reg_ofs = 0x900,
.bd_ram_ofs = 0x2000,
.mac_control = (1 << 5),
.control = cpsw_control,
.host_port_num = 0,
.version = CPSW_CTRL_VERSION_2,
};
#endif
/*
* This function will:
* Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
* in the environment
* Perform fixups to the PHY present on certain boards. We only need this
* function in:
* - SPL with either CPSW or USB ethernet support
* - Full U-Boot, with either CPSW or USB ethernet
* Build in only these cases to avoid warnings about unused variables
* when we build an SPL that has neither option but full U-Boot will.
*/
#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) \
&& defined(CONFIG_SPL_BUILD)) || \
((defined(CONFIG_DRIVER_TI_CPSW) || \
defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) && \
!defined(CONFIG_SPL_BUILD))
int board_eth_init(bd_t *bis)
{
int rv, n = 0;
uint8_t mac_addr[6];
uint32_t mac_hi, mac_lo;
__maybe_unused struct am335x_baseboard_id header;
int type = 0;
/* try reading mac address from efuse */
mac_lo = readl(&cdev->macid0l);
mac_hi = readl(&cdev->macid0h);
mac_addr[0] = mac_hi & 0xFF;
mac_addr[1] = (mac_hi & 0xFF00) >> 8;
mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
mac_addr[4] = mac_lo & 0xFF;
mac_addr[5] = (mac_lo & 0xFF00) >> 8;
#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
if (!getenv("ethaddr")) {
printf("<ethaddr> not set. Validating first E-fuse MAC\n");
if (is_valid_ethaddr(mac_addr))
eth_setenv_enetaddr("ethaddr", mac_addr);
}
#ifdef CONFIG_DRIVER_TI_CPSW
mac_lo = readl(&cdev->macid1l);
mac_hi = readl(&cdev->macid1h);
mac_addr[0] = mac_hi & 0xFF;
mac_addr[1] = (mac_hi & 0xFF00) >> 8;
mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
mac_addr[4] = mac_lo & 0xFF;
mac_addr[5] = (mac_lo & 0xFF00) >> 8;
if (!getenv("eth1addr")) {
if (is_valid_ethaddr(mac_addr))
eth_setenv_enetaddr("eth1addr", mac_addr);
}
if (read_eeprom(&header) < 0)
puts("Could not get board ID.\n");
if (board_is_bone(&header) || board_is_bone_lt(&header) ||
board_is_idk(&header)) {
writel(MII_MODE_ENABLE, &cdev->miisel);
cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
PHY_INTERFACE_MODE_MII;
} else if (board_is_uc8100a(&header)) {
#if 0
type = (GMII1_SEL_RMII | GMII2_SEL_RMII | RGMII1_IDMODE| RGMII2_IDMODE \
| RMII1_IO_CLK_EN | RMII2_IO_CLK_EN);
writel(type, &cdev->miisel);
cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RMII;
#endif
writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII;
} else {
type = (GMII1_SEL_RMII | GMII2_SEL_RMII | RGMII1_IDMODE| RGMII2_IDMODE \
| RMII1_IO_CLK_EN | RMII2_IO_CLK_EN);
writel(type, &cdev->miisel);
cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RMII;
}
rv = cpsw_register(&cpsw_data, 2);
if (rv < 0)
printf("Error %d registering CPSW switch\n", rv);
else
n += rv;
#endif
/*
*
* CPSW RGMII Internal Delay Mode is not supported in all PVT
* operating points. So we must set the TX clock delay feature
* in the AR8051 PHY. Since we only support a single ethernet
* device in U-Boot, we only do this for the first instance.
*/
#define AR8051_PHY_DEBUG_ADDR_REG 0x1d
#define AR8051_PHY_DEBUG_DATA_REG 0x1e
#define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
#define AR8051_RGMII_TX_CLK_DLY 0x100
if (board_is_evm_sk(&header) || board_is_gp_evm(&header)) {
const char *devname;
devname = miiphy_get_current_dev();
miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
AR8051_DEBUG_RGMII_CLK_DLY_REG);
miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
AR8051_RGMII_TX_CLK_DLY);
}
#endif
#if defined(CONFIG_USB_ETHER) && \
(!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
if (is_valid_ethaddr(mac_addr))
eth_setenv_enetaddr("usbnet_devaddr", mac_addr);
rv = usb_eth_initialize(bis);
if (rv < 0)
printf("Error %d registering USB_ETHER\n", rv);
else
n += rv;
#endif
return n;
}
#endif
#endif /* CONFIG_DM_ETH */
BR Rio
