No interrupts on VDINT0

Deepika

Hi All,

I am working on customized board based on DM355 SoC, in which I have to capture 16bit YCbCr data in 1024x768 and 1920x1080 resolution. I have modified CCDC driver (davinci_vpfe.c/ cccdc_dm355.c files) for the same, but unable to get interrupts. I have configured PINMUX0 setting to 0x7F55 and HD/VD sync signal will be external, so configured as input. PCLK is 74.18MHz (I won't be using H3A module).CAM_WEN_FIELD signal will be used to indicate even/odd field.

Below is the register dump of CCDC:

Reading 0x0 to SYNCEN...

Reading 0x9080 to MODESET...

Reading 0x0 to HDWIDTH...

Reading 0x0 to VDWIDTH...

Reading 0x0 to PPLN...

Reading 0x0 to LPFR...

Reading 0x0 to SPH...

Reading 0xeff to NPH...

Reading 0x0 to SLV0...

Reading 0x0 to SLV1...

Reading 0x21b to NLV...

Reading 0xffff to CULH...

Reading 0xff to CULV...

Reading 0x78 to HSIZE...

Reading 0x249 to SDOFST...

Reading 0x0 to STADRH...

Reading 0x0 to STADRL...

Reading 0x0 to CLAMP...

Reading 0x0 to DCSUB...

Reading 0x0 to COLPTN...

Reading 0x0 to BLKCMP0...

Reading 0x0 to BLKCMP1...

Reading 0x0 to MEDFILT...

Reading 0x80 to RYEGAIN...

Reading 0x80 to GRCYGAIN...

Reading 0x80 to GBGGAIN...

Reading 0x80 to BMGGAIN...

Reading 0x0 to OFFSET...

Reading 0xfff to OUTCLIP...

Reading 0x0 to VDINT0...

Reading 0x0 to VDINT1...

Reading 0x0 to RSV0...

Reading 0x0 to GAMMAWD...

Reading 0x0 to REC656IF...

Reading 0x8840 to CCDCFG...

Reading 0x0 to FMTCFG...

Reading 0x0 to FMTPLEN...

Reading 0x0 to FMTSPH...

Reading 0x0 to FMTLNH...

Reading 0x0 to FMTSLV...

Reading 0x0 to FMTLNV...

Reading 0x0 to FMTRLEN...

Reading 0x0 to FMTHCNT...

Reading 0x0 to FMT_ADDR_PTR_B...

Reading 0x0 to FMTPGM_VF0...

Reading 0x0 to FMTPGM_VF1...

Reading 0x0 to FMTPGM_AP0...

Reading 0x0 to FMTPGM_AP1...

Reading 0x0 to FMTPGM_AP2...

Reading 0x0 to FMTPGM_AP3...

Reading 0x0 to FMTPGM_AP4...

Reading 0x0 to FMTPGM_AP5...

Reading 0x0 to FMTPGM_AP6...

Reading 0x0 to FMTPGM_AP7...

Reading 0x0 to LSCCFG1...

Reading 0x0 to LSCCFG2...

Reading 0x0 to LSCH0...

Reading 0x0 to LSCV0...

Reading 0x0 to LSCKH...

Reading 0x0 to LSCKV...

Reading 0x0 to LSCMEMCTL...

Reading 0x0 to LSCMEMD...

Reading 0x0 to LSCMEMQ...

Reading 0x0 to DFCCTL...

Reading 0x0 to DFCVSAT...

Reading 0x0 to DFCMEMCTL...

Reading 0x0 to DFCMEM0...

Reading 0x0 to DFCMEM1...

Reading 0x0 to DFCMEM2...

Reading 0x0 to DFCMEM3...

Reading 0x0 to DFCMEM4...

Reading 0x0 to CSCCTL...

Reading 0x0 to CSCM0...

Reading 0x0 to CSCM1...

Reading 0x0 to CSCM2...

Reading 0x0 to CSCM3...

Reading 0x0 to CSCM4...

Reading 0x0 to CSCM5...

Reading 0x0 to CSCM6...

Reading 0x0 to CSCM7...

Reading 0x0 to DATAOFST...

I don't know why I am unable to receive interrupts, i have probed the CAM_HD/CAM_VD/CAM_ WEN_FIELD/PCLK signals and everything seems correct over there.

Am I missing anything or is there something wrong in understanding/implementation??

Any kind of help will be appreciated.

Thanks & Regards,

Deepika

over 16 years ago

0 Deepika over 16 years ago

Prodigy 125 points

Hi All,

VPFE datasheet (spruf71.pdf) section 5.4.3.1 indicates that "VDINT0 and VDINT1 will occur after receiving the
number of horizontal lines (HD pulse signals) set in the VDINT.VDINT0 and VDINT.VDINT1 register fields,
respectively" while when I looked at the CCDC and vpfe driver code, I found:

vert_start = image_win->top;

   if (frm_fmt == CCDC_FRMFMT_INTERLACED) {
      vert_nr_lines = (image_win->height >> 1) - 1;
      vert_start >>= 1;
      /* configure VDINT0 and VDINT1 */
      regw(vert_start, VDINT0);
   } else {
      vert_nr_lines = image_win->height - 1;
      /* configure VDINT0 and VDINT1 */
      mid_img = vert_start + (image_win->height / 2);
      regw(vert_start, VDINT0);
      regw(mid_img, VDINT1);
   }

image_win top, is zero in my case, so it leads to 0x0 in VDINT0. Am I doing something wrong over here?

Thanks

Deepika

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No interrupts on VDINT0