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Linux/AM3359: DDR frequency not changing

Part Number: AM3359

Tool/software: Linux

Hello all,

                             I'm trying to reduce the DDR frequency to 303 from 400 MHz.We modified this function in board.c :

config_ddr(303, &ioregs_evmsk, &ddr3_icev2_data,
                           &ddr3_icev2_cmd_ctrl_data, &ddr3_icev2_emif_reg_data,
                           0);
 

                                   But when we probed the DDR clock with oscilloscope the frequency is still 400MHz.

                                  We investigated further an found that the function which actually should set the frequency is empty(emif4.c).

void __weak ddr_pll_config(unsigned int ddrpll_m)
{

}
 

                                      How can I change the frequency?

Regards,

Murugan S

  • Hello,

    Please refer to the following page as a reference.

    Regards,
    Krunal

  • Hi Krunal,

                       I already went through that document several times before.In the document its mentioned that  to change ddr frequency i have to use this function:

    config_ddr(303, &ioregs_evmsk, &ddr3_icev2_data,
                               &ddr3_icev2_cmd_ctrl_data, &ddr3_icev2_emif_reg_data,
                               0);

                  As I mentioned before the function which is supposed to use the 303 value is blank.

    Im attaching the code segment here:

    void __weak ddr_pll_config(unsigned int ddrpll_m)
    {

    }

    void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
                    const struct ddr_data *data, const struct cmd_control *ctrl,
                    const struct emif_regs *regs, int nr)
    {
            ddr_pll_config(pll);
            config_vtp(nr);
            config_cmd_ctrl(ctrl, nr);

            config_ddr_data(data, nr);

    #ifdef CONFIG_AM33XX

            config_io_ctrl(ioregs);

            /* Set CKE to be controlled by EMIF/DDR PHY */
            writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);

    #endif
    #ifdef CONFIG_AM43XX
            writel(readl(&cm_device->cm_dll_ctrl) & ~0x1, &cm_device->cm_dll_ctrl);
            while ((readl(&cm_device->cm_dll_ctrl) & CM_DLL_READYST) == 0)
                    ;

            config_io_ctrl(ioregs);

            /* Set CKE to be controlled by EMIF/DDR PHY */
            writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);

            if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3)
    #ifndef CONFIG_SPL_RTC_ONLY_SUPPORT
                    /* Allow EMIF to control DDR_RESET */

                    writel(0x00000000, &ddrctrl->ddrioctrl);
    #else
                    /* Override EMIF DDR_RESET control */
                    writel(0x80000000, &ddrctrl->ddrioctrl);
    #endif /* CONFIG_SPL_RTC_ONLY_SUPPORT */
    #endif


            /* Program EMIF instance */
            config_ddr_phy(regs, nr);

            set_sdram_timings(regs, nr);
            if (get_emif_rev(EMIF1_BASE) == EMIF_4D5)

           config_sdram_emif4d5(regs, nr);
            else
                    config_sdram(regs, nr);
    }

    Regards,

    Murugan S

  • Please add a printf inside the config_ddr() function to print out the pll parameter that was passed to it.  You're correct that to change the DDR frequency, you simply need to pass the desired frequency to the config_ddr() function.  I expect you have a mistake somewhere with respect to how the function is being called (e.g. being called multiple times or being called with wrong frequency, etc.).

  • Hi Brad,

                             Thanks for your input.But my doubt is:

    1)DDR frequency is set using this function:

    config_ddr(303, &ioregs_evmsk, &ddr3_icev2_data,&ddr3_icev2_cmd_ctrl_data, &ddr3_icev2_emif_reg_data, 0);

    2)Inside config_ddr() function pll frequency(303 in my case) is used by  ddr_pll_config(pll) function.

    3)But ddr_pll_config(pll) is an empty function.It does nothing.

                      This is my observation.Did i miss anything?

    Regards,

    Murugan S

  • Murugan,

    I'm sorry, you're right!  I'm not sure if the method changed at some point or if I was perhaps thinking of a different family of devices.  I'll make a revision to my prior post to cross out my incorrect statement.

    In any case, there's a function in board.c called get_dpll_ddr_params().  That's where the DDR frequency is configured.

    Best regards,
    Brad