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AM3505: SYS_CLK startup time requirements

Brian Normand
Prodigy 40 points

Part Number: AM3505
Other Parts Discussed in Thread: TPS65910,

A bit of background info : the 26 MHz sys_clk is generated by an external oscillator, which is enabled when sys_clkreq asserts from the Sitara.

Observing on Oscope, sys_clkreq asserts ( active  high ) nearly the same time the NRESPWRON de-asserts ( active low )

We also use the power management chip TPS65910. We are in bypass mode as sysboot[6] pulled high.

Question:  the 26MHz sys_clk oscillator has changed startup time specs from 2ms to 8ms ( Abracon AP3S2-26MHz ). Another second-source oscillator has a 10ms out enable delay ( pericom )… is either case a problem ? I How long after reset de-asserts should the 26MHz be stable ? 

  • 0
    TI__Guru 64335 points

    When using an external square wave clock source that is gated by the SYS_CLKREQ signal, the clock source is expected to produce a clean start reference that has stable frequency and duty cycle without any short cycles (no glitches).

     

    The start time of this reference clock relative to the release of NRESPWRON is not important as long as the requirements stated above are met.

     

    Regards,

    Paul

  • 0 in reply to peaves
    TI__Expert 3550 points

    It would be the very first clock pulse after output enable (sys_clk_req ) that is possibly shortened pulse or runt ….

    The Sitara will not handle this ? What happens ?


  • 0 in reply to Egon Hirsch
    TI__Guru 64335 points

    A short clock pulse may over-clock synchronous circuits in the AM3505 devices which can create unpredictable results.

    You could avoid any concern associated with a short clock cycle by tying the oscillator enable high and holding the AM3505 device in reset until the oscillator output is stable. However, this topology requires the system oscillator power supply pin (VDDSOSC) to be powered at the same time or before the external LVCMOS oscillator since the SYS_XTALIN pin is not fail-safe. Power supply sequencing will not be an issue if VDDSOSC pin is sourced from the same power supply that is used to source the external LVCMOS oscillator.

    Regards,
    Paul

  • 0 in reply to peaves
    Prodigy 40 points

    I can do that... thanks for your help

    Brian