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some problem about VPFE of dm355



 

H i ,everyone.

W hen  I  debug the Generic YUV mode of DM355 VPFE,I find a problem.

The  image input to dm355 is produced By FPGA(it get the image from the VGA signal of PC via a video decoder),the PCLK is 65MHz.CCD0~CCD7 is  Y,

and  CCD8~CCD15 is Cb/Cr.

T he right image is like this:

 

B ut the image which is get by the  application  of the DM355 is like this:  

 

Y ou can see the frame of the window have some  protraction .

I n the  beginning   I   doubt  that the  waveform  of the FPGA is wrong ,but if I make the Cb/Cr 0x80

( i.e.  CCD15~CCD8 is always 1000 0000B,the image is gray )

and change nothing else,the image get by the  application  of the DM355 have no  protraction .

it is like this(I think it can show that the  waveform  of the FPGA is right):

 

 

T hen  I  make the Y 0x80( i.e.  CCD7~CCD0 is always 1000 0000B ,

 CCD15~CCD8 is the Cb/Cr of the image)and change nothing else,

the image also have no  protraction .it is like this:

 

I think there is something wrong in the  matching  between dm355 and the FPGA . 

this is my configuration of the dm355 vpfe register, help me please,thanks!!!!!

 

Reading 0x0 to SYNCEN...

Reading 0x1000 to MODESET...

Reading 0x0 to HDWIDTH...

Reading 0x0 to VDWIDTH...

Reading 0x0 to PPLN...

Reading 0x0 to LPFR...

Reading 0x0 to SPH...

Reading 0x3ff to NPH...

Reading 0x0 to SLV0...

Reading 0x0 to SLV1...

Reading 0x2ff to NLV...

Reading 0xffff to CULH...

Reading 0xff to CULV...

Reading 0x40 to HSIZE...

Reading 0x0 to SDOFST...

Reading 0x0 to STADRH...

Reading 0x0 to STADRL...

Reading 0x0 to CLAMP...

Reading 0x0 to DCSUB...

Reading 0x0 to COLPTN..

Reading 0x0 to BLKCMP0...

Reading 0x0 to BLKCMP1...

Reading 0x0 to MEDFILT...

Reading 0x100 to RYEGAIN...

Reading 0x100 to GRCYGAIN...

Reading 0x100 to GBGGAIN...

Reading 0x100 to BMGGAIN...

Reading 0x0 to OFFSET...

Reading 0x3fff to OUTCLIP...

Reading 0x0 to VDINT0...

Reading 0x0 to VDINT1...

Reading 0x0 to RSV0...

Reading 0x0 to GAMMAWD...

Reading 0x0 to REC656IF...

Reading 0x8800 to CCDCFG...

Reading 0x0 to FMTCFG...

Reading 0x0 to FMTPLEN...

Reading 0x0 to FMTSPH...

Reading 0x0 to FMTLNH...

Reading 0x0 to FMTSLV...

Reading 0x0 to FMTLNV...

Reading 0x0 to FMTRLEN...

Reading 0x0 to FMTHCNT...

Reading 0x0 to FMT_ADDR_PTR_B...

Reading 0x0 to FMTPGM_VF0...

Reading 0x0 to FMTPGM_VF1...

Reading 0x0 to FMTPGM_AP0...

Reading 0x0 to FMTPGM_AP1...

Reading 0x0 to FMTPGM_AP2...

Reading 0x0 to FMTPGM_AP3...

Reading 0x0 to FMTPGM_AP4...

Reading 0x0 to FMTPGM_AP5...

Reading 0x0 to FMTPGM_AP6...

Reading 0x0 to FMTPGM_AP7...

Reading 0x0 to LSCCFG1...

Reading 0x0 to LSCCFG2...

Reading 0x0 to LSCH0...

Reading 0x0 to LSCV0...

Reading 0x0 to LSCKH...

Reading 0x0 to LSCKV...

Reading 0x10 to LSCMEMCTL...

Reading 0x0 to LSCMEMD...

Reading 0x0 to LSCMEMQ...

Reading 0x0 to DFCCTL...

Reading 0x0 to DFCVSAT...

Reading 0x0 to DFCMEMCTL...

Reading 0x0 to DFCMEM0...

Reading 0x0 to DFCMEM1...

Reading 0x0 to DFCMEM2...

Reading 0x0 to DFCMEM3...

Reading 0x0 to DFCMEM4...

Reading 0x0 to CSCCTL...

Reading 0x0 to CSCM0...

Reading 0x0 to CSCM1...

Reading 0x0 to CSCM2...

Reading 0x0 to CSCM3...

Reading 0x0 to CSCM4...

Reading 0x0 to CSCM5...

Reading 0x0 to CSCM6...

Reading 0x0 to CSCM7...

Reading 0x0 to DATAOFST...

 

  • Based on your captures I have doubts that this is a configuration problem between the FPGA and the VPFE, your output image looks like there is some signal instability, as if you are getting crosstalk somewhere in the hardware. Is the connection between the FPGA and the FPFE all on a single PCB or do you have this running over a cable or connector of some sort? Is the video clock signal very clean?

    It is interesting that the image comes across properly if half of the bus is kept constant as you were doing, do you get similar noise artifacts if you have the FPGA generate patterns other than a constant 0x80 on half of the bus?

  • This looks like an hardware signalling problem, ie when you have some amount of change on all your data bus, you have crosstalk or reflection. I suggest trying the following :
    changing PCLK frequency if it is possible.
    using a color pattern to have clear edges, and thus be eventually able to monitor data with a scope.
    moving only half of the byte (for example all Y bit and four MSB of color), or the opposite.