AM5726: Three QSPI flash connections

shigehiro tsuda

Part Number: AM5726

Hi,

Our customer will use three QSPI flash.
Which is the correct schematic of connecting QSPI_SCLK and QSPI_RTCLK?
There was one connection, but there was no connection for multiple use in the AM572x datasheet.
Figure 8-30. QSPI Interface High Level Schematic

The following is described in TRM. When using in MODE 3, is QSPI_RTCLK loopback not required?

Table 24-355. QSPI I/O Signals
In case Mode 3 is used, there is no need to connect the qspi1_sclk to the qspi1_rtclk.

case1:

case2:

Best Regards,
Shigehiro Tsuda

over 7 years ago

0 melissaw over 7 years ago

TI__Genius 16030 points

Hi Tsuda-San,

I am looking into your question and will follow up soon.

Regards,

Melissa

0 shigehiro tsuda over 7 years ago in reply to melissaw

Mastermind 9490 points

Hi Melissa,

Thank you for quick reply.

Is there any update information?
Since our customer is considering the system, I want this answer as soon as possible.

Best Regards,
Shigehiro Tsuda

0 melissaw over 7 years ago in reply to shigehiro tsuda

TI__Genius 16030 points

Hi Tsuda-san,

The purpose of the RCLK is for read timing. Its delay should match the delay of the SCLK to the memory device, PLUS the delay of the data from the memory device to the SOC.

Therefore, routing the RCLK through the buffer (Case 1) would be correct as an attempt to match the delay. However, I’m not sure how the signal integrity would look in this configuration. From the image below, I assume only one ‘buffer’ device can be enabled at any one time?

Case 2 might work if all the delays to each memory device where matched. Otherwise, delays would be matched to 1 device, but not for the other 2 devices.

As stated in the TRM, the QSPI_RTCLK loopback is not required for Mode 3.

Regards,

Melissa

0 shigehiro tsuda over 7 years ago in reply to melissaw

Mastermind 9490 points

Hi Melissa,

Thank you for quick reply.

Case 1:
Yes, I assume only one buffer is enabled.
Other buffers are considered to be high impedance control.

Case 2:
The layout is assumed to make all delays as same as possible.

Case 3:
Do not use RCLK using MODE3.

Which do you consider the best?

Best Regards,
Shigehiro Tsuda

0 Brad Griffis over 7 years ago in reply to shigehiro tsuda

TI__Guru*** 125430 points

Mode 0 is the fastest, but do you need the fastest? Given the need for multiple devices, there's a cost in using the fastest (i.e. cost and space of additional logic). In my view, there is a trade off between having "fastest" solution or "simplest/cheapest" solution. If the simple solution is fast enough (48 MHz QSPI), then I recommend using it.

0 shigehiro tsuda over 7 years ago in reply to Brad Griffis

Mastermind 9490 points

Hi Brad,

Thank you for quick reply.
Our customer seems to want to use at 48MHz or higher.
Which is best in case1 or case2?
Please answer if there is another good idea.

Best Regards,
Shigehiro Tsuda

0 shigehiro tsuda over 7 years ago in reply to Brad Griffis

Mastermind 9490 points

Hi Brad,

Is there any update information?

Our customers are having trouble in circuit design.
I want an answer as soon as possible.

Best Regards,
Shigehiro Tsuda

0 shigehiro tsuda over 7 years ago in reply to Brad Griffis

Mastermind 9490 points

Hi Brad,

Thank you for your support.

The following connection is asked by our customer.

They think that the influence of the reflection will be reduced if the clock signal is wired with one stroke so as to make the stub as short as possible.
Is such a connection a problem?

Best Regards,
Shigehiro Tsuda

0 Brad Griffis over 7 years ago in reply to shigehiro tsuda

TI__Guru*** 125430 points

If 48MHz is sufficiently fast, use the simplified topology I suggested.

0 shigehiro tsuda over 7 years ago in reply to Brad Griffis

Mastermind 9490 points

Hi Brad,

Thank you for quick reply.
Which connection is the simplified topology you suggested for use with a 48MHz fast clock?

Best Regards,
Shigehiro Tsuda

0 Brad Griffis over 7 years ago in reply to shigehiro tsuda

TI__Guru*** 125430 points

Mode 3 without RTCLK.

0 shigehiro tsuda over 7 years ago in reply to Brad Griffis

Mastermind 9490 points

Hi Brad,

Thank you for quick reply.

Our customer's product specifications need to be accessed as fast as possible (max 76.8MHz).
Therefore, the request is a connection using RTCLK in MODE0.
I asked a few cases, which one is better?

Best Regards,
Shigehiro Tsuda

0 Brad Griffis over 7 years ago in reply to shigehiro tsuda

TI__Guru*** 125430 points

There is no definitive correct answer. This is a judgment call that ultimately should be made by the customer.

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AM5726: Three QSPI flash connections