66AK2H06: how to set exception propely?

YaoTing Mao

Intellectual 540 points

Part Number: 66AK2H06
Other Parts Discussed in Thread: SYSBIOS

Hi all,

how to i set the exception properly with CSL?

i try to use the same way with normal interrupt but it doesn't work.

here is my code

int eventIDNMI[] = // CIC module output to INTC module input
{
CSL_C66X_COREPAC_TIMER_11_INTL,

};

_IntcVectId vectIDNMI[] =

{
CSL_INTC_VECTID_EXCEP,
CSL_INTC_VECTID_7,

};

hIntcNMI[0] = CSL_intcOpen(&intcObj, eventIDNMI[0], &vectIDNMI[0], NULL);

CSL_intcHookIsr(vectIDNMI[0], NMI_ISR_handler[0]); // Hook the ISR's

CSL_intcHwControl(hIntcNMI[0], CSL_INTC_CMD_EVTCLEAR,NULL); // Clear any pending interrupts

CSL_intcHwControl(hIntcNMI[0], CSL_INTC_CMD_EVTENABLE,NULL); // Clear any pending interrupts

then i set the register TSR to enable it.

Uint32 chipReg[1];

chipReg[0] = CSL_chipReadReg (CSL_CHIP_TSR);
CSL_chipWriteReg (CSL_CHIP_TSR, chipReg[0] | 0x0000000c); // enable all exception

I want to use timer 11 to trigger exception but if it doesn't work.

it is ok to use CSL_INTC_VECTID_7 for the normal interrupt but I want the DSP can use CSL_INTC_VECTID_EXCEP for the exception.

Does anyone know how to set exception properly?

Thanks

over 7 years ago

0 lding over 7 years ago

TI__Guru* 95265 points

Hi,

There is a Keystone interrupt wiki: http://processors.wiki.ti.com/index.php/Configuring_Interrupts_on_Keystone_Devices. You can see that

The C66x DSP provides two types of asynchronous signaling services: Interrupts and Exceptions. Interrupts provide the means to redirect normal program flow due to the presence of an external or internal hardware signal. Exceptions are similar in that they also redirect program flow, but they are normally associated with error conditions in the system. The C66x DSP can receive 12 maskable/configurable interrupts, 1 maskable exception, and 1 unmaskable interrupt/exception. The C66x CorePac interrupt controller INTC allows up to 124 system events to be routed to the DSP interrupt/exception inputs. These 124 events can either be directly connected to the maskable interrupts, or grouped together as interrupts or exceptions. [2]

The figure below shows the CorePac INTC [2]. The 124 event IDs are represented by EVT[127:4], and the 12 maskable/configurable interrupts are represented by INTC[15:4].

The exception combiner is routed to CPU exception.

From CSL,

/** Should be used at the time of opening an Event handle
* to specify that the event needs to go to the exception
* combiner.
*/
CSL_INTC_VECTID_EXCEP = 17

We don't have a complete CSL code example for exception, but you can refer to packages\ti\csl\src\intc\csl_intcHwControl.c, CSL_intcExcepEnable() as a starting point. There is some timer interrupt example under ti\csl\example\timer\timer_test.c

Regards, Eric

0 YaoTing Mao over 7 years ago in reply to lding

Intellectual 540 points

Hi Eric,

I am still confused about the exception setup.

From TMS320C66x DSP CorePac User Guide (SPRUGW0C), page 9-3, figure 9-1, the exception input is from Exception combiner.

Does it mean it need to use csl_intcHwControl twice?

The first time: invoke CSL_intcHwControl to setup EXPMASK register.

the 2nd time: invoke CSL_intcHwControl to setup CSL_intcCombinedEventEnable ?

Thank for the response.

YaoTing

0 lding over 7 years ago in reply to YaoTing Mao

TI__Guru* 95265 points

Hi,

I thought you need to call CSL_intcHwControl to enable CSL_intcExcepEnable(hIntc->eventId), that is achieved by passing CSL_INTC_CMD_EVTENABLE and vectId = 17.

I don't have the whole complete code sequence for this. Another way is to use the SYSBIOS, add below in the .cfg file:

var exception = xdc.useModule('ti.sysbios.family.c64p.Exception');
exception.enablePrint = true;

Regards, Eric

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66AK2H06: how to set exception propely?