Hello,
Are there any requirements on the relationship between VCLK and MCLK - or can I use any input values that I can work out using the appropriate PLLs and dividers? For example, could I have a CPU clock of 300MHz (i.e. VCLK would be 150MHz) and setup PLL1 to divide by 3 to get an MCLK at 100MHz?
Thanks,
Katie
