Part Number: 66AK2H14
Hello
I have a question for my understanding of how the DDR (or DDR memory controller) works.
Let’s say that we have a keystone I or keystone II processor.
Let’s suppose we use L2 memory as RAM and not cache.
For these architectures from my understanding and tests,
The cache (L1D) is of type “write around”
Which to me means that :
- If an address is not in the cache, the data is written to the address and not in the cache.
- A subsequent read at that address would cause a “cache miss” (the data is not in the cache), and the data will be fetched from physical memory
Q1) is this understanding correct ?
Then let’s move to two use cases :
a)
- I have disabled cacheability in the DDR address range (through MAR registers)
- I never read data in DDR, I only write data
- I measure speed performances : they are low, a couple hundreds of MB/s
b)
- I have enabled cacheability in the DDR address range (through MAR registers)
- I never read data in DDR, I make sure the DDR address range is not in cache, I only write data to the DDR address range
- I measure speed performances : they are much better, with several thousand of MB/s
In b) as no data is in the cache and because the cache is of type “write around”, I write directly in DDR memory. So the cache is not used. However performances are very different.
Q2) how do you explain such a big difference in performances ?
Thank you
Regards
Clement
