RTOS/AM5746: Data abort questions

rei

Part Number: AM5746
Other Parts Discussed in Thread: AM5749

Tool/software: TI-RTOS

Hi,
My customers are using a custom board with AM5746.
When frequent GPMC access, the phenomenon that ARM core data aborts occurred.
We think that it's related to Eratta's i878, and we have the following questions.

Question 1:
If a hangup of Eratta i 878 occurs, will the ARM core abort the data?
They wonder if the phenomenon that is happening now matches the phenomenon of i878.

DFSR register : 0x00000211

DFSR Register.pdf

Question 2:
There is a statement about 0x482AF400 as a workaround of Eratta i878.
However, the details of this register are not described in TRM.
What kind of register is it?
Please let me know if you have detailed information such as documents.

Question 3:
I got the ARM core register information from customers when the phenomenon occurred.
Is it related to the hangup phenomenon of Eratta i878?
There is also the possibility of causes other than i878, so please let me know if there are other factors.
(If you do not have enough information to identify the cause, please let me know.)

ARM Registers (ABORT).pdf

Fullscreen MMU_Table_List.txt Download

__________address________|_physical________________|sec|_d_|_size____|_permissions__________________________|_glb|_shr|_pageflags_(remapped)___________|
     N:00000000--007FFFFF| AN:00:00000000--007FFFFF| ns|   | 00200000| P:readonly  U:readonly   P:ex   U:ex | yes| no | strongly ordered               |
     N:00800000--00FFFFFF| AN:00:88200000--889FFFFF| ns|   | 00200000| P:readwrite U:readwrite  P:xn   U:xn | yes| out| non-cacheable                  |
     N:01000000--017FFFFF| AN:00:01000000--017FFFFF| ns|   | 00200000| P:readonly  U:readonly   P:ex   U:ex | yes| no | strongly ordered               |
     N:01800000--049FFFFF| AN:00:88A00000--8BBFFFFF| ns|   | 00200000| P:readwrite U:readwrite  P:xn   U:xn | yes| out| write-back/read-write-allocate |
     N:04A00000--04FFFFFF| AN:00:04A00000--04FFFFFF| ns|   | 00200000| P:readonly  U:readonly   P:ex   U:ex | yes| no | strongly ordered               |
     N:05000000--053FFFFF| AN:00:81600000--819FFFFF| ns|   | 00200000| P:readwrite U:readwrite  P:ex   U:ex | yes| out| write-back/read-write-allocate |
     N:05400000--057FFFFF| AN:00:05400000--057FFFFF| ns|   | 00200000| P:readonly  U:readonly   P:ex   U:ex | yes| no | strongly ordered               |
     N:05800000--05BFFFFF| AN:00:87A00000--87DFFFFF| ns|   | 00200000| P:readwrite U:readwrite  P:ex   U:ex | yes| out| write-back/read-write-allocate |
     N:05C00000--05FFFFFF| AN:00:05C00000--05FFFFFF| ns|   | 00200000| P:readonly  U:readonly   P:ex   U:ex | yes| no | strongly ordered               |
     N:06000000--06BFFFFF| AN:00:83600000--841FFFFF| ns|   | 00200000| P:readwrite U:readwrite  P:xn   U:xn | yes| out| write-back/read-write-allocate |
     N:06C00000--06FFFFFF| AN:00:06C00000--06FFFFFF| ns|   | 00200000| P:readonly  U:readonly   P:ex   U:ex | yes| no | strongly ordered               |
     N:07000000--073FFFFF| AN:00:81600000--819FFFFF| ns|   | 00200000| P:readwrite U:readwrite  P:ex   U:ex | yes| out| write-back/read-write-allocate |
     N:07400000--077FFFFF| AN:00:87A00000--87DFFFFF| ns|   | 00200000| P:readwrite U:readwrite  P:ex   U:ex | yes| out| write-back/read-write-allocate |
     N:07800000--07BFFFFF| AN:00:07800000--07BFFFFF| ns|   | 00200000| P:readonly  U:readonly   P:ex   U:ex | yes| no | strongly ordered               |
     N:07C00000--07DFFFFF| AN:00:10000000--101FFFFF| ns|   | 00200000| P:readwrite U:readwrite  P:xn   U:xn | yes| out| device                         |
     N:07E00000--07FFFFFF| AN:00:07E00000--07FFFFFF| ns|   | 00200000| P:readonly  U:readonly   P:ex   U:ex | yes| no | strongly ordered               |
     N:08000000--083FFFFF| AN:00:19000000--193FFFFF| ns|   | 00200000| P:readwrite U:readwrite  P:xn   U:xn | yes| out| device                         |
     N:08400000--087FFFFF| AN:00:19000000--193FFFFF| ns|   | 00200000| P:readwrite U:readwrite  P:xn   U:xn | yes| out| device                         |
     N:08800000--08FFFFFF| AN:00:08800000--08FFFFFF| ns|   | 00200000| P:readonly  U:readonly   P:ex   U:ex | yes| no | strongly ordered               |
     N:09000000--09FFFFFF| AN:00:1A000000--1AFFFFFF| ns|   | 00200000| P:readwrite U:readwrite  P:xn   U:xn | yes| out| device                         |
     N:0A000000--0A3FFFFF| AN:00:19800000--19BFFFFF| ns|   | 00200000| P:readwrite U:readwrite  P:xn   U:xn | yes| out| device                         |
     N:0A400000--0A7FFFFF| AN:00:19800000--19BFFFFF| ns|   | 00200000| P:readwrite U:readwrite  P:xn   U:xn | yes| out| device                         |
     N:0A800000--0ABFFFFF| AN:00:1D000000--1D3FFFFF| ns|   | 00200000| P:readwrite U:readwrite  P:xn   U:xn | yes| out| device                         |
     N:0AC00000--0AFFFFFF| AN:00:0AC00000--0AFFFFFF| ns|   | 00200000| P:readonly  U:readonly   P:ex   U:ex | yes| no | strongly ordered               |
     N:0B000000--0BFFFFFF| AN:00:1B000000--1BFFFFFF| ns|   | 00200000| P:readwrite U:readwrite  P:xn   U:xn | yes| out| device                         |
     N:0C000000--0C9FFFFF| AN:00:88A00000--893FFFFF| ns|   | 00200000| P:readwrite U:readwrite  P:xn   U:xn | yes| out| write-back/read-write-allocate |
     N:0CA00000--0FFFFFFF| AN:00:8C200000--8F7FFFFF| ns|   | 00200000| P:readwrite U:readwrite  P:ex   U:ex | yes| out| write-back/read-write-allocate |
     N:10000000--103FFFFF| AN:00:10000000--103FFFFF| ns|   | 00200000| P:readwrite U:readwrite  P:xn   U:xn | yes| no | device                         |
     N:10400000--11FFFFFF| AN:00:10400000--11FFFFFF| ns|   | 00200000| P:readonly  U:readonly   P:xn   U:xn | yes| no | device                         |
     N:12000000--129FFFFF| AN:00:12000000--129FFFFF| ns|   | 00200000| P:readwrite U:readwrite  P:xn   U:xn | yes| no | device                         |
     N:12A00000--137FFFFF| AN:00:12A00000--137FFFFF| ns|   | 00200000| P:readonly  U:readonly   P:ex   U:ex | yes| no | strongly ordered               |
     N:13800000--139FFFFF| AN:00:13800000--139FFFFF| ns|   | 00200000| P:readwrite U:readwrite  P:xn   U:xn | yes| out| device                         |
     N:13A00000--17FFFFFF| AN:00:13A00000--17FFFFFF| ns|   | 00200000| P:readonly  U:readonly   P:ex   U:ex | yes| no | strongly ordered               |
     N:18000000--18FFFFFF| AN:00:18000000--18FFFFFF| ns|   | 00200000| P:readwrite U:readwrite  P:xn   U:xn | yes| no | device                         |
     N:19000000--191FFFFF| AN:00:19000000--191FFFFF| ns|   | 00200000| P:readwrite U:readwrite  P:xn   U:xn | yes| out| device                         |
     N:19200000--197FFFFF| AN:00:19200000--197FFFFF| ns|   | 00200000| P:readonly  U:readonly   P:xn   U:xn | yes| no | device                         |
     N:19800000--199FFFFF| AN:00:19800000--199FFFFF| ns|   | 00200000| P:readwrite U:readwrite  P:xn   U:xn | yes| out| device                         |
     N:19A00000--19FFFFFF| AN:00:19A00000--19FFFFFF| ns|   | 00200000| P:readonly  U:readonly   P:xn   U:xn | yes| no | device                         |
     N:1A000000--1BFFFFFF| AN:00:1A000000--1BFFFFFF| ns|   | 00200000| P:readwrite U:readwrite  P:xn   U:xn | yes| out| device                         |
     N:1C000000--1CFFFFFF| AN:00:1C000000--1CFFFFFF| ns|   | 00200000| P:readonly  U:readonly   P:ex   U:ex | yes| no | strongly ordered               |
     N:1D000000--1D1FFFFF| AN:00:1D000000--1D1FFFFF| ns|   | 00200000| P:readwrite U:readwrite  P:xn   U:xn | yes| out| device                         |
     N:1D200000--1D7FFFFF| AN:00:1D200000--1D7FFFFF| ns|   | 00200000| P:readonly  U:readonly   P:xn   U:xn | yes| no | device                         |
     N:1D800000--1D9FFFFF| AN:00:1D800000--1D9FFFFF| ns|   | 00200000| P:readwrite U:readwrite  P:xn   U:xn | yes| out| device                         |
     N:1DA00000--1DFFFFFF| AN:00:1DA00000--1DFFFFFF| ns|   | 00200000| P:readonly  U:readonly   P:xn   U:xn | yes| no | device                         |
     N:1E000000--3FFFFFFF| AN:00:1E000000--3FFFFFFF| ns|   | 00200000| P:readwrite U:readwrite  P:xn   U:xn | yes| out| device                         |
     N:40000000--403FFFFF| AN:00:40000000--403FFFFF| ns|   | 00200000| P:readwrite U:readwrite  P:ex   U:ex | yes| out| device                         |
     N:40400000--405FFFFF| AN:00:40400000--405FFFFF| ns|   | 00200000| P:readwrite U:readwrite  P:xn   U:xn | yes| out| device                         |
     N:40600000--407FFFFF|                         |   |   |         |                                      |    |    |                                |
     N:40800000--423FFFFF| AN:00:40800000--423FFFFF| ns|   | 00200000| P:readwrite U:readwrite  P:xn   U:xn | yes| out| device                         |
     N:42400000--42BFFFFF| AN:00:42400000--42BFFFFF| ns|   | 00200000| P:readonly  U:readonly   P:xn   U:xn | yes| no | device                         |
     N:42C00000--42FFFFFF| AN:00:42C00000--42FFFFFF| ns|   | 00200000| P:readwrite U:readwrite  P:xn   U:xn | yes| out| device                         |
     N:43000000--431FFFFF| AN:00:43000000--431FFFFF| ns|   | 00200000| P:readonly  U:readonly   P:xn   U:xn | yes| no | device                         |
     N:43200000--433FFFFF| AN:00:43200000--433FFFFF| ns|   | 00200000| P:readwrite U:readwrite  P:xn   U:xn | yes| no | device                         |
     N:43400000--435FFFFF| AN:00:43400000--435FFFFF| ns|   | 00200000| P:readwrite U:readwrite  P:xn   U:xn | yes| out| device                         |
     N:43600000--43FFFFFF| AN:00:43600000--43FFFFFF| ns|   | 00200000| P:readonly  U:readonly   P:xn   U:xn | yes| no | device                         |
     N:44000000--47FFFFFF| AN:00:44000000--47FFFFFF| ns|   | 00200000| P:readwrite U:readwrite  P:xn   U:xn | yes| out| device                         |
     N:48000000--483FFFFF| AN:00:48000000--483FFFFF| ns|   | 00200000| P:readwrite U:noaccess   P:xn   U:xn | yes| no | strongly ordered               |
     N:48400000--48FFFFFF| AN:00:48400000--48FFFFFF| ns|   | 00200000| P:readwrite U:readwrite  P:ex   U:ex | yes| no | strongly ordered               |
     N:49000000--49FFFFFF| AN:00:49000000--49FFFFFF| ns|   | 00200000| P:readwrite U:readwrite  P:xn   U:xn | yes| out| device                         |
     N:4A000000--4A1FFFFF| AN:00:4A000000--4A1FFFFF| ns|   | 00200000| P:readwrite U:noaccess   P:xn   U:xn | yes| no | strongly ordered               |
     N:4A200000--4ADFFFFF| AN:00:4A200000--4ADFFFFF| ns|   | 00200000| P:readwrite U:readwrite  P:xn   U:xn | yes| out| device                         |
     N:4AE00000--4AFFFFFF| AN:00:4AE00000--4AFFFFFF| ns|   | 00200000| P:readwrite U:readwrite  P:ex   U:ex | yes| no | strongly ordered               |
     N:4B000000--7FFFFFFF| AN:00:4B000000--7FFFFFFF| ns|   | 00200000| P:readwrite U:readwrite  P:xn   U:xn | yes| out| device                         |
     N:80000000--825FFFFF| AN:00:80000000--825FFFFF| ns|   | 00200000| P:readwrite U:readwrite  P:ex   U:ex | yes| out| write-back/read-write-allocate |
     N:82600000--827FFFFF| AN:00:82600000--827FFFFF| ns|   | 00200000| P:readwrite U:readwrite  P:xn   U:xn | yes| out| write-back/read-write-allocate |
     N:82800000--829FFFFF| AN:00:82800000--829FFFFF| ns|   | 00200000| P:readwrite U:readwrite  P:xn   U:xn | yes| out| non-cacheable                  |
     N:82A00000--835FFFFF| AN:00:82A00000--835FFFFF| ns|   | 00200000| P:readwrite U:readwrite  P:xn   U:xn | yes| out| write-back/read-write-allocate |
     N:83600000--841FFFFF| AN:00:83600000--841FFFFF| ns|   | 00200000| P:readwrite U:readwrite  P:xn   U:xn | yes| out| non-cacheable                  |
     N:84200000--85BFFFFF| AN:00:84200000--85BFFFFF| ns|   | 00200000| P:readwrite U:readwrite  P:xn   U:xn | yes| out| write-back/read-write-allocate |
     N:85C00000--8FFFFFFF| AN:00:85C00000--8FFFFFFF| ns|   | 00200000| P:readwrite U:readwrite  P:ex   U:ex | yes| out| write-back/read-write-allocate |
     N:90000000--91DFFFFF| AN:00:85C00000--879FFFFF| ns|   | 00200000| P:readwrite U:readwrite  P:ex   U:ex | yes| out| write-back/read-write-allocate |
     N:91E00000--9FFFFFFF| AN:00:91E00000--9FFFFFFF| ns|   | 00200000| P:readwrite U:noaccess   P:ex   U:ex | yes| inn| write-back/read-write-allocate |
     N:A0000000--A03FFFFF| AN:00:08000000--083FFFFF| ns|   | 00200000| P:readwrite U:readwrite  P:ex   U:ex | yes| no | device                         |
     N:A0400000--A7FFFFFF| AN:00:08400000--0FFFFFFF| ns|   | 00200000| P:readwrite U:readwrite  P:xn   U:xn | yes| no | device                         |
     N:A8000000--BFFFFFFF| AN:00:A8000000--BFFFFFFF| ns|   | 00200000| P:readonly  U:readonly   P:ex   U:ex | yes| no | strongly ordered               |
     N:C0000000--CFFFFFFF| AN:00:80000000--8FFFFFFF| ns|   | 00200000| P:readwrite U:readwrite  P:ex   U:ex | yes| out| non-cacheable                  |
     N:D0000000--FFFFFFFF| AN:00:D0000000--FFFFFFFF| ns|   | 00200000| P:readonly  U:readonly   P:ex   U:ex | yes| no | strongly ordered               |

Question 4:
There are many possible causes for the DFSR register to become 0x00000211.
What is the cause of the data abort that occurred this time?

■Environment
CCS v8
GCC GNU v6.3.1(Linaro)
HW Custom board (AM5746)
SW pdk_am57xx_1_0_11
bios_6_52_00_12
XDCTools 3.50.3.33

Regards,
Rei

over 6 years ago

0 melissaw over 6 years ago

TI__Genius 15920 points

Hi Rei,

I am looking into your question and will follow up next week.

Regards,

Melissa

0 rei over 6 years ago in reply to melissaw

Mastermind 6155 points

Hi Melissa,
Thank you for your reply.

We look forward to information,
It is additional information.
I also uploaded the DECERR Register.

DECERR Registers.pdf

Regards,
Rei

0 rei over 6 years ago in reply to rei

Mastermind 6155 points

Hi Melissa,
I'm sorry many times, it is additional information.
Summary of DMM register information before and after error(STDERRLOG).
I compared partial register information of L3_Main.

Comparison result.pdf

Fullscreen L3I_STDERRLOG_before.txt Download

________address|________0________4________8________C________0________4________8________C_0123456789ABCDEF0123456789ABCDEF
   NSD:44000000|>001A0001 0070D13F 00000004 00000000 00000000 00000000 00000000 00000000 ....?.p.........................
   NSD:44000020| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:44000040| 00000002 00000002 00080003 00100000 0000000C 00000020 00000000 00000000 .................... ...........
   NSD:44000060| 00000000 00000000 000000C4 00000000 00000020 00000000 00000000 00000000 ................ ...............
   NSD:44000080| ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ????????????????????????????????
   NSD:440000A0| ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ????????????????????????????????
   NSD:440000C0| ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ????????????????????????????????
   NSD:440000E0| ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ????????????????????????????????
   NSD:44000100| 00130001 00478E81 00000001 00000000 0000000C 00000000 00000000 00000000 ......G.........................
   NSD:44000120| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:44000140| 00000002 00000002 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:44000160| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:44000180| 0000001F 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:440001A0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:440001C0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:440001E0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:44000200| 00130001 000FC6F8 00000001 00000000 00000002 00000000 00000000 00000000 ................................
   NSD:44000220| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:44000240| 00000002 00000002 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:44000260| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:44000280| 0000001F 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:440002A0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:440002C0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:440002E0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:44000300| 00130001 00FB8051 00000001 00000000 00000004 00000000 00000000 00000000 ....Q...........................
   NSD:44000320| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:44000340| 00000002 00000002 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:44000360| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:44000380| 0000001F 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:440003A0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:440003C0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:440003E0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:44000400| ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ????????????????????????????????
   NSD:44000420| ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ????????????????????????????????
   NSD:44000440| ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ????????????????????????????????
   NSD:44000460| ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ????????????????????????????????
   NSD:44000480| ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ????????????????????????????????
   NSD:440004A0| ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ????????????????????????????????
   NSD:440004C0| ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ????????????????????????????????
   NSD:440004E0| ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ????????????????????????????????
   NSD:44000500| 00130001 009E6840 00000001 00000000 00000014 00000000 00000000 00000000 ....@h..........................
   NSD:44000520| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:44000540| 00000002 00000002 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:44000560| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:44000580| 0000001F 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:440005A0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:440005C0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:440005E0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:44000600| 00130001 00EB1855 00000001 00000000 00000005 00000000 00000000 00000000 ....U...........................
   NSD:44000620| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:44000640| 00000002 00000002 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:44000660| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:44000680| 0000001F 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:440006A0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................

Fullscreen L3I_STDERRLOG_after.txt Download

________address|________0________4________8________C________0________4________8________C_0123456789ABCDEF0123456789ABCDEF
   NSD:44000000|>001A0001 0070D13F 00000004 00000000 00000000 00000000 00000000 00000000 ....?.p.........................
   NSD:44000020| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:44000040| 00000002 00000002 00080003 00100000 0000000C 00000020 00000000 00000000 .................... ...........
   NSD:44000060| 00000000 00000000 000000C4 00000000 00000020 00000000 00000000 00000000 ................ ...............
   NSD:44000080| ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ????????????????????????????????
   NSD:440000A0| ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ????????????????????????????????
   NSD:440000C0| ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ????????????????????????????????
   NSD:440000E0| ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ????????????????????????????????
   NSD:44000100| 00130001 00478E81 00000001 00000000 0000000C 00000000 00000000 00000000 ......G.........................
   NSD:44000120| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:44000140| 00000002 00000002 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:44000160| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:44000180| 0000001F 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:440001A0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:440001C0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:440001E0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:44000200| 00130001 000FC6F8 00000005 00000000 00000002 00000000 00000000 00000000 ................................
   NSD:44000220| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:44000240| 00000002 00000002 00080003 00000002 00000018 00000040 00000000 00000000 ....................@...........
   NSD:44000260| 00000000 000000C4 00000000 00000002 00000000 00000000 00000000 00000000 ................................
   NSD:44000280| 0000001F 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:440002A0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:440002C0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:440002E0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:44000300| 00130001 00FB8051 00000001 00000000 00000004 00000000 00000000 00000000 ....Q...........................
   NSD:44000320| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:44000340| 00000002 00000002 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:44000360| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:44000380| 0000001F 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:440003A0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:440003C0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:440003E0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:44000400| ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ????????????????????????????????
   NSD:44000420| ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ????????????????????????????????
   NSD:44000440| ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ????????????????????????????????
   NSD:44000460| ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ????????????????????????????????
   NSD:44000480| ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ????????????????????????????????
   NSD:440004A0| ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ????????????????????????????????
   NSD:440004C0| ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ????????????????????????????????
   NSD:440004E0| ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ????????????????????????????????
   NSD:44000500| 00130001 009E6840 00000001 00000000 00000014 00000000 00000000 00000000 ....@h..........................
   NSD:44000520| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:44000540| 00000002 00000002 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:44000560| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:44000580| 0000001F 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:440005A0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:440005C0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:440005E0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:44000600| 00130001 00EB1855 00000001 00000000 00000005 00000000 00000000 00000000 ....U...........................
   NSD:44000620| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:44000640| 00000002 00000002 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:44000660| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:44000680| 0000001F 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................
   NSD:440006A0| 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ................................

Would you tell me if it is involved in i878?

Regards,
Rei

0 melissaw over 6 years ago in reply to rei

TI__Genius 15920 points

Hi Rei,

Can you share how frequently this data abort occurs? Also, do you see the issue occur at run-time or boot?

Regards,

Melissa

0 rei over 6 years ago in reply to melissaw

Mastermind 6155 points

Hi Melissa,

Not necessarily, but they seem to be occurring frequently.
And a data abort occurs at runtime.

It is checked for both GPMC and EMIF (DDR), and this issue is occurring.
If you do not check GPMC(check only DDR), the frequency of data aborts seems to be reduced. (Still occurre)

Regards,
Rei

0 Hideaki Matsumoto over 6 years ago in reply to melissaw

TI__Genius 9230 points

Hi Melissa,

Thank you for looking into this issue. The issue occurred at run-time. Actual frequency has not yet been measured, but it happens when GPMC and EMIF are accessed very often, like a RAM check of unused area in GPMC and EMIF DDR.

We have to figure out a root cause and fix it ASAP. Any advice would be helpful.

Thanks and regards,
Hideaki

0 melissaw over 6 years ago in reply to Hideaki Matsumoto

TI__Genius 15920 points

Thanks for the extra details. Between the customer's issue occurring at run-time and the ARM DFSR register being accessible, it's very unlikely that i878 is the root cause of this issue. (With i878, the ARM "locks up" with no access and the ARM DFSR register would not be readable.)

The DFSR value the customer gives decodes to an alignment fault. If they observed this value at a data abort, they should check the LR at the time of the exception to map it back to what instruction was just executed. If they dumped the registers at a random time (not in abort mode), there might not be much meaning.

This doesn’t appear to be a processor lock up. Maybe the ARM took an abort but that’s not a hang to the ARM, even if it is to some higher level application.

Regards,

Melissa

0 rei over 6 years ago in reply to melissaw

Mastermind 6155 points

Hi Melissa,

I asked my customers, these are not alignment faults.
Because they use "Long-descriptor translation table format".(Not Short-descriptor)
We think that it applies to Table 4-61, "Asynchronous external abort".

Would you tell me if you have any advice for the i878's possibilities or other factors?

Regards,
Rei

0 melissaw over 6 years ago in reply to rei

TI__Genius 15920 points

Rei,

Thanks for this clarification. The fact that they can read the DFAR register at all implies that it's not related to i878.

The fact that the ARM saw an ‘async ext abort’ does say that at least 1 of the pending L3 errors was caused by the ARM itself.

On an interconnect/L3 error, an SRESP (async event) is sent back to the host which caused the issue (if one can be determined). It will then raise an L3-interrupt on the GIC (sync to the L3 source issuer). The ARM typically gets notified with the L3-irq when ‘someone’ triggers an L3 fault, it will also get the SRESP (async-imprecise bus error) when it generated the event. Some ‘bad’ ARM code will mask the ‘CPSR.A’ bit to ignore async abort (and also may mask the L3 irq) as a way to ignore the events. This is not recommended especially in development time. In production maybe you can characterize and rationalize an error but that should be the exception not the rule.

Regards,

Melissa

0 Garrett Ding over 6 years ago in reply to rei

TI__Mastermind 43296 points

Rei,

From the code snippet shown in the ARM Registers (ABORT).pdf, the exception seemed to happen during the data structure inpMngTbl initialization, and the data structure is allocated from EMIF DDR. Errata i878 is applicable only when there are concurrent accesses to the DDR address space via the Low Latency path and the L3 Interconnect path. Is there any DMA access to the memory concurrently? And why GPMC is in the picture?

Can you please elaborate the use case? This doesn't seem to be a simple memory stress test. If this is a TI-RTOS application on A15, MMU is configured as LPAE, and the exception code 0x211 in DFSR does indicate an "Asynchronous external abort". The 'FS Alignment' in above DFSR register.pdf is misleading, was this interpreted by any tool?

Due to the natural of asynchronous external abort, the address in (R14 - 8) might not exactly point to the exception instruction 'ldr r3,[r11,#-0x1c]'. When the exception occurs, does the R14 always show the same location 0x8118FE40? If yes, have you tried to add memory barrier asm (" dsb") to see if the exception moves away? You may try to add after inpMngTbl->nTimeout = apAddInfo->mTimeout as well.

And is the issue also reproducible on AM5749 IDK?

Regards,

Garrett

0 Garrett Ding over 6 years ago in reply to Garrett Ding

TI__Mastermind 43296 points

Also as noted in i878 errata, 'The MPU_MA register is a valid register address location even though it is located outside the MPU memory space as specified in the device TRM.' have you tried to set MPU_MA register at 0x482AF400 bits 2 and 1, that is, 0x482AF400 |= 0x6?

Regards,

Garrett

0 rei over 6 years ago in reply to Garrett Ding

Mastermind 6155 points

Thank you for a lot of information.
I organized the information.

■ Melissa-san said "With i 878, the ARM" locks up "with no access and the ARM DFSR register would not be readable."
We can read the DFSR registers, so we thought that the cause was other than i878.
(Supplement: 0x482AF400 | = 0x6 had no effect.)

■ Because there is an FS field, it looks like a short-descriptor.
This is a debugger (Lauterbach) specification.
In fact they use Long-descriptor.

■ This issue has not been reproduced with AM574xIDK.
This phenomenon does not occur by simply accessing the unused area of DDR.
Therefore I think that there are various factors.

Summarize the questions
Question 1:
Please see the previous reply material.
・ Comparison result. Pdf
・ L3I_STDERRLOG_before.txt
・ L3I_STDERRLOG_after.txt

The value of the DMM register changes before and after a data abort.
Would you tell me the meaning and cause of the change of the register value.

Question 2:
Would you tell me the cause of "Asynchronous external abort" (DFSR = 0x211) of DMM path.

Any information is our salvation.

Regards,
Rei

0 melissaw over 6 years ago in reply to rei

TI__Genius 15920 points

Hi Rei-san,

I’ve reviewed the mentioned files with a colleague, and we don’t see any additional useful information. The customer needs to collect information about the errors differently to have any chance of converging on a root cause.

The device TRM gives a 'typical error analysis" flow chart in the Interconnect chapter which must be followed.

There are several layers of information in this sequence, and each layer has some partial information. After processing all the layers, ‘sometimes’ it’s clear what the error was and sometimes not. With the error information, it is usually possible in the lab to use the JTAG tools find the error.

Regards,

Melissa

0 rei over 6 years ago in reply to melissaw

Mastermind 6155 points

Thank you for the information.
I read :
・Figure 14-8. Typical Error Analysis Sequence
・14.2.3.8.5 Example for Decoding Standard/Custom Errors Logged in L3_MAIN

////////////////////////////////////
Read L3_TARG_STDERRLOG_MSTADDR[7:0] STDERRLOG_MSTADDR - > 8-bit NTTP master
address used to distinguish the different initiators (see Table 14-10). That master address is also
referred to as ConnID or MConnID.
////////////////////////////////////

STDERRLOG_MSTADDR are 0x18. (L3I_STDERRLOG_after.txt)
However, there is no description in Table 14-10.
What do you indicate?

Regards,
Rei

0 melissaw over 6 years ago in reply to rei

TI__Genius 15920 points

Hi Rei,

Looking in L3I_STDERRLOG_after.txt, I see that the error is a “Custom Error.” Bit 1 (STDERRLOG_MAIN_ERRTYPE) in 0x44000048 = 1.

The STDERRLOG_MSTADDR and Table 15-10 only has meaning for a “Standard error” type. Standard errors are events where the interconnect shoots down the transaction at launch and the TARG captures info in registers. Custom errors happen after the stream is already accepted and running. They are signaled by the target. The TARG can only capture some response information at the error. The MSTADDR is not available during these later phases of the transfer.

The 0x18 value needs to be << 1 when looking at Table 15-10 and therefore, corresponds to DSP2_CFG (0x18 << 1 = 0x30). However, as indicated above, this field could be misdirecting in the debug since the error is a custom error.

I’ve reached out to a colleague for tips when debugging custom errors. Hope to have more comments tomorrow.

Regards,

Melissa

0 rei over 6 years ago in reply to melissaw

Mastermind 6155 points

Hi Melissa,

Thank you for your reply.

We look forward to your custom error information.

Also we are also looking for other solutions.

To solve "Asynchronous external abort" (DFSR = 0x211), are there any other registers to check?

Regards,

Rei

0 melissaw over 6 years ago in reply to rei

TI__Genius 15920 points

Hi Rei,

I am closing this thread, as the conversation has moved to e-mail.

Regards,

Melissa

0 Hideaki Matsumoto over 6 years ago

TI__Genius 9230 points

Part Number: AM5746

Tool/software: TI-RTOS

Hi,

In the debugging the Data Abort issue, the customer found that the reason why Data Abort Exception occurred every time on their source codes because Abit of CPSR was set when Arm core moved to IRQ mode. (We don’t know the reason why, but Abort Exception was disabled.)

Why Abort Exception is masked in IRQ mode ?

Could you tell us how to enable always Abort Exception, not masked ?

Regards,

Hideaki

0 melissaw over 6 years ago in reply to Hideaki Matsumoto

TI__Genius 15920 points

Hi Matsumoto-san,

The following Arm link includes the answers to the customer's questions-- http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0344k/Beiieecf.html.

Regards,

Melissa

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RTOS/AM5746: Data abort questions