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RTOS/TMS320C6678: inter-core DDR memory allocation and modification anomaly

Shlomi Fraiman
Prodigy 80 points

Part Number: TMS320C6678

Tool/software: TI-RTOS

Hi,

i'm running different applications on different (0 to 7) cores of the C6678 DSP ant noticed very strange issue as described below:

1. while on one core (for example core 1) i allocate memorry (using "new") the object is allocated to the address 0x80001fc0

2. while core 0 is running, on core 1 executed the allocation mentioned in #1 and allocated memory is zeroed (memset).

3. while the memory allocated is zeroed - the core 0 is crushing.

4. while debugging i noticed that when i change the value at 0x80001fc0 on core 1 happens some strange things:

a. the value at 0x80001fc0 is not changing on set command. only on 2nd or 3rd time it finally changes.

b. when the value finally changes - this value is reflected (modified) in all other cores at the same address (0x80001fc0) (same on next addresses)

c. when trying to modify the value of the address  4 bytes before (0x80001fbc) the value updated in each core separately and wasn't modified in this address (0x80001fbc) in other cores. (same on addresses before 0x80001fbc)

5. the problem is consistent and repeats every time.

what is so special about the address 0x80001fc0 (before or after)?

if this addresses are special or reserved, why the OS allocates it for user objects?

how can i solve this issue?

Please advice,

Thanks in advance!

Shlomi

  • 0
    TI__Guru**** 161600 points

    Hi,

    The address space 80000000 to FFFFFFFF is DDR3 EMIF data, as per Table 2-2Memory Map Summary (Sheet 7 of 7) in the Device Datasheet. There shouldn't be anything special aobut the address 80001fc0.

    How is this address space defined in your linker.cmd?  Also do you access the same memory location (80001fc0) from different cores at the same time?

    Best Regards,
    Yordan

  • 0 in reply to Yordan Kovachev
    Prodigy 80 points

    in r linker.cmd defined:

    MEMORY
    {
    L2SRAM (RWX) : org = 0x800000, len = 0x80000
    MSMCSRAM (RWX) : org = 0xc000000, len = 0x400000
    DDR3 : org = 0x80000000, len = 0x20000000
    }

    i do access the same memory location from different cores at the same time, but in some locations (as described above) it seems that the memory is isolated to each core, while in others memory locations (as described) it is not.

  • 0 in reply to Shlomi Fraiman
    TI__Guru**** 161600 points

    Hi,

    i do access the same memory location from different cores at the same time, but in some locations (as described above) it seems that the memory is isolated to each core, while in others memory locations (as described) it is not.

    I think this would depend on how your separate linker.cmd & .cfg files for each applications are constructed. Can you try using a shared memory location for your apps (as you run them on different cores), if possible?

    Best Regards,
    Yordan