Hello Everyone,
after having some problems on activating digital BT.656 output, I want to share my experiences by writing a short guide about it.
This guide is based on dvsk_1_30_00_40 and mv_pro_4.0.1. Delivered sourcecode has not been tested with other versions, but should be compatible. It will show how to activate BT.656 output so it is available for the evm demos and psp examples.
First step: Follow the "Getting Starded Guide" 4.5 and 4.7. This is necessary to confirm that your development enviroment works and your able to boot from TFTP.
Second step: Open */ti-davinci/drivers/media/video/davinci/davinci_platform.c
Third step: Edit the following Functions like this:
(red lines show changes)
static void enableDigitalOutput(int bEnable)
{
if (bEnable) {
dispc_reg_out(VENC_VMOD, 0);
dispc_reg_out(VENC_CVBS, 0);
if (!cpu_is_davinci_dm355()) {
davinci_writel(0, (DM644X_VPBE_REG_BASE + VPBE_PCR));
}
dispc_reg_out(VENC_LCDOUT, 0);
dispc_reg_out(VENC_HSPLS, 0);
dispc_reg_out(VENC_HSTART, 0);
dispc_reg_out(VENC_HVALID, 0);
dispc_reg_out(VENC_HINT, 0);
dispc_reg_out(VENC_VSPLS, 0);
dispc_reg_out(VENC_VSTART, 0);
dispc_reg_out(VENC_VVALID, 0);
dispc_reg_out(VENC_VINT, 0);
dispc_reg_out(VENC_YCCCTL, 0);
dispc_reg_out(VENC_DACSEL, 0);
} else {
/* Initialize the VPSS Clock Control register */
davinci_writel(0x18, SYS_VPSS_CLKCTL);
davinci_writel(0, (DM644X_VPBE_REG_BASE + VPBE_PCR));
/* Set PINMUX0 reg to enable LCD (all other settings are kept
per boot)
*/
if (!cpu_is_davinci_dm355()) {
davinci_cfg_reg(DM644X_LOEEN);
davinci_cfg_reg(DM644X_LFLDEN);
}
/*reset video encoder module*/
dispc_reg_out(VENC_VMOD,0);
/* disable VCLK output pin enable */
dispc_reg_out(VENC_VIDCTL, 0x141);
/* Disable output sync pins */
dispc_reg_out(VENC_SYNCCTL, 0);
/* Disable DCLOCK */
dispc_reg_out(VENC_DCLKCTL, 0);
dispc_reg_out(VENC_DRGBX1, 0x0000057C);
/* Disable LCD output control (accepting default polarity) */
dispc_reg_out(VENC_LCDOUT, 0);
if (!cpu_is_davinci_dm355()) {
dispc_reg_out(VENC_CMPNT, 0x100);
}
dispc_reg_out(VENC_HSPLS, 0);
dispc_reg_out(VENC_HINT, 0);
dispc_reg_out(VENC_HSTART, 0);
dispc_reg_out(VENC_HVALID, 0);
dispc_reg_out(VENC_VSPLS, 0);
dispc_reg_out(VENC_VINT, 0);
dispc_reg_out(VENC_VSTART, 0);
dispc_reg_out(VENC_VVALID, 0);
dispc_reg_out(VENC_HSDLY, 0);
dispc_reg_out(VENC_VSDLY, 0);
//dispc_reg_out(VENC_YCCCTL, 0);
dispc_reg_out(VENC_VSTARTA, 0);
/* set VIDCTL to select VCLKE=1,VCLKZ=0,SYDIR=0,DMOD=0,YCSWP=0 */
dispc_reg_out(VENC_VIDCTL, 0x6000); // vclk enable, 0x2000 for valid data on falling edge
/*set REC656 Mode*/
dispc_reg_out(VENC_YCCCTL,0x0001); // set digital output to bt.646 mode
/*show color bar on screen */
//dispc_reg_out(VENC_VDPRO, 0x0903); // use this to display color bar on screen (usefull 4 debugging)
/* Set OSD clock and OSD Sync Adavance registers */
dispc_reg_out(VENC_OSDCLK0, 1);
dispc_reg_out(VENC_OSDCLK1, 2);
}
}
/*
* setting NTSC mode
*/
static void davinci_enc_set_ntsc(struct vid_enc_mode_info *mode_info)
{
enableDigitalOutput(0);
if (cpu_is_davinci_dm355()) {
dispc_reg_out(VENC_CLKCTL, 0x11); // activate lcd controller clk
/*configure VMOD*/
dispc_reg_out(VENC_VMOD,0x1003); // change bit 1 for disabling analog output
//dispc_reg_out(VENC_VIDCTL, 0);
/* DM 350 Configure VDAC_CONFIG , why ?? */
davinci_writel(0x0E21A6B6, DM355_VDAC_CONFIG);
} else {
/* to set VENC CLK DIV to 1 - final clock is 54 MHz */
dispc_reg_merge(VENC_VIDCTL, 0, 1 << 1);
/* Set REC656 Mode */
dispc_reg_out(VENC_YCCCTL, 0x1);
dispc_reg_merge(VENC_VDPRO, 0, VENC_VDPRO_DAFRQ);
dispc_reg_merge(VENC_VDPRO, 0, VENC_VDPRO_DAUPS);
}
if (cpu_is_davinci_dm355()) {
davinci_writel(mode_info->left_margin,
(DM355_OSD_REG_BASE + OSD_BASEPX));
davinci_writel(mode_info->upper_margin,
(DM355_OSD_REG_BASE + OSD_BASEPY));
} else {
davinci_writel(mode_info->left_margin,
(DM644X_OSD_REG_BASE + OSD_BASEPX));
davinci_writel(mode_info->upper_margin,
(DM644X_OSD_REG_BASE + OSD_BASEPY));
}
dispc_reg_merge(VENC_VMOD, VENC_VMOD_VENC, VENC_VMOD_VENC);
}
/*
* setting PAL mode
*/
static void davinci_enc_set_pal(struct vid_enc_mode_info *mode_info)
{
enableDigitalOutput(0);
if (cpu_is_davinci_dm355()) {
dispc_reg_out(VENC_CLKCTL, 0x11); // activate lcd controller
/*configure VMOD*/
dispc_reg_out(VENC_VMOD,0x1043); // change bit 1 for disabling analog output
//dispc_reg_out(VENC_VIDCTL, 0);
/* DM350 Configure VDAC_CONFIG */
davinci_writel(0x0E21A6B6, DM355_VDAC_CONFIG);
} else {
/* to set VENC CLK DIV to 1 - final clock is 54 MHz */
dispc_reg_merge(VENC_VIDCTL, 0, 1 << 1);
/* Set REC656 Mode */
dispc_reg_out(VENC_YCCCTL, 0x1);
}
dispc_reg_merge(VENC_SYNCCTL, 1 << VENC_SYNCCTL_OVD_SHIFT,
VENC_SYNCCTL_OVD);
if (cpu_is_davinci_dm355()) {
davinci_writel(mode_info->left_margin,
(DM355_OSD_REG_BASE + OSD_BASEPX));
davinci_writel(mode_info->upper_margin,
(DM355_OSD_REG_BASE + OSD_BASEPY));
} else {
davinci_writel(mode_info->left_margin,
(DM644X_OSD_REG_BASE + OSD_BASEPX));
davinci_writel(mode_info->upper_margin,
(DM644X_OSD_REG_BASE + OSD_BASEPY));
}
dispc_reg_merge(VENC_VMOD, VENC_VMOD_VENC, VENC_VMOD_VENC);
dispc_reg_out(VENC_DACTST, 0x0);
}
Fourth step: delete "davinci_platform.o" and compile a new kernel like 4.5 in GSG
Fivth step: Run the new kernel like 4.7 in GSG
I hope this could help you. Feel free to tell your experiences with my Guide.
Josef Kohler