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66AK2H06: High Speed Serial Interfaces

abhishek srivastava13
Prodigy 70 points

Part Number: 66AK2H06

1. Can i configure ethernet switch of the 66AK2H06 processor such that all the devices connected to port1 to port 4 can not send data among them i.e Data from any device connected on ethernet with processor can not send data to other device. All the dara first received on port0 and then 66AK2H06 (ARM0) device will route data as per it's choice. I don't want to configure the Gb Ethernet switch as a switch. All the host devices can send data to port0 only which will be accessed by ARM/DSP and then ARM/DSP will decide about data.

2. I want to use PCIe/SRIO/Hyperlink for data exchange. I want to know if i can use all mentioned interfaces on any DSP or ARM.

3. In a case, i want to use 66AK2H06 device in Non-RTOS environment. Is it possible to use all interfaces and capabilities of the device as mentioned in data sheet?

  • 0
    TI__Guru* 95265 points

    Hi,

    1. Yes, in CPSW module, the ALE may be configured to operate in bypass mode by setting the ALE_BYPASS bit in the ALE_CONTROL Register. When in bypass mode, all packets received by the MAC modules are forwarded only to the host port (port 0). 

    2. For Processor SDK RTOS, there are drivers for PCIE, SRIO and Hyperlink on DSP core. For ARM, the way to run those interface is through Linux. There are old MCSDK Linux package have them supported, but the package was obsolete and replaced by Processor SDK Linux. In Processor SDK Linux, those drivers are still there. Among them, SRIO and Hyperlink are not actively maintained and tested. 

    3. Yes, you can run those bare-metal or your own OS.

    Regards, Eric

  • 0 in reply to lding
    Prodigy 70 points

    I want to connect 66AK2H06 with zynq device on pcie..Only these two devices...Do i need to configure any device as a pcie root complex...Or as an end point they can exchange data..

  • 0 in reply to abhishek srivastava13
    TI__Guru* 95265 points

    Hi,

    You need to configure one as PCIE RC and the other as PCIE EP.

    Regards, Eric