Hi,
The customer configured SRIO working with 1×LaneA and 2×LaneAB, But the values of PLM_SP(n)_PATH_CTL are 1024 and 1025. It seems the value of bit Path_config are always be configured to 4 lanes.
I have found this post https://e2e.ti.com/support/processors/f/791/p/452311/1627862 was the same doubt. And at the end of the post tscheck said Path_config is read only from the user perspective. It is set by tie-offs at the device level. Don't attempt to write it. It should always read '4'.
Does it mean that the value of Path_config will not be changed regardless of the configuration? Please help give some advice.
